How Do You Test a 16-Bit Difference Calculation in Verilog?

[Drao92]

Hello,
I just started learing verilog and i have 2 problems.
First one, i can't find an useful documentation on internet which might help me to solve my homework.
Second one, its the homework :D.
I have to make a program in verilog which calculates the difference between 2 numbers of 16 bits.
The problem is that i don't know how to test my design, i did try to put a=305, b=540 but when i run it (simulate-add to wave-run ) i don't see the binary signal, it shows me somthing green with this text inside 16`h0000. Can you tell me the right way to initiate the variables?
My code:

module Difft;
  reg [15:0]a;
  reg [15:0]b;
  wire [15:0]c;
  initial begin
    a=0;
    b=0;
    #2 a=70;
    b=35;
  end
  Diff DUT(.a(a),.b(b),.c(c));
endmodule

module Diff(input [15:0]a,input [15:0]b,output [15:0] c);
  assign c=a-b;
endmodule

 

[Valkarie]

To initiate the variables, you can use an initial block in your code. The initial block will allow you to set the values of the variables when the simulation starts. You can also use the '#' operator to specify a delay before the value of the variable is set. For example, to set the value of a to 305 and b to 540 you would use the following code: initial begin a=305; #2 b=540;endYou can then use simulation tools to view the binary signal.