- #1
PainterGuy
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- TL;DR Summary
- Some questions about the text on interrupts and bus request operations.
Hi,
Could you please help me with the queries below?
Please have a look on this attachment.
Question 1:
It says, "Because the processor cannot know when an interrupt will occur, it automatically saves on the register stack status information about the program that is executing at the time the interrupt or exception occurs."
In my opinion, the text suggests that the processor always keeps itself ready to serve an interrupt, in other words it's always expecting an interrupt, but then it suggests something somewhat contradictory that the processor saves information at the time the interrupt occurs.
Question 2:
The text also says, "Software reset This is a software exception and is sometimes called a warm boot. This also restarts the system but bypasses many of the hardware initialization tasks performed by a cold boot."
I also checked online and found the following definition. I believe that software reset or warm boot refers to the RESTART from START MENU on Windows computer. I had always thought that the software reset clear all the contents of memory because your computer does start afresh and you can't find any trace of previously running program(s).
warm boot
Reloading the operating system by performing a Restart operation from the computer's main menu while it is still turned on. The warm boot does not turn the power off and back on, and it does not clear memory. Contrast with cold boot.
Source: https://www.pcmag.com/encyclopedia/term/54212/warm-boot
Question 3:
Now please have a look on this attachment.
It says, "Secondly, in a bus request operation, the processor passes control of the system buses to the requesting device, which then handles all bus operations. The processor continues to execute instructions in the ISR or exception handler during interrupts."
If the processor passes control of all the buses to the requesting device then how could it keep on executing instructions in the ISR or exception handler during interrupts? Doesn't it need to regain the control of buses back to serve the interrupts?
Thank you for your help!
Could you please help me with the queries below?
Please have a look on this attachment.
Question 1:
It says, "Because the processor cannot know when an interrupt will occur, it automatically saves on the register stack status information about the program that is executing at the time the interrupt or exception occurs."
In my opinion, the text suggests that the processor always keeps itself ready to serve an interrupt, in other words it's always expecting an interrupt, but then it suggests something somewhat contradictory that the processor saves information at the time the interrupt occurs.
Question 2:
The text also says, "Software reset This is a software exception and is sometimes called a warm boot. This also restarts the system but bypasses many of the hardware initialization tasks performed by a cold boot."
I also checked online and found the following definition. I believe that software reset or warm boot refers to the RESTART from START MENU on Windows computer. I had always thought that the software reset clear all the contents of memory because your computer does start afresh and you can't find any trace of previously running program(s).
warm boot
Reloading the operating system by performing a Restart operation from the computer's main menu while it is still turned on. The warm boot does not turn the power off and back on, and it does not clear memory. Contrast with cold boot.
Source: https://www.pcmag.com/encyclopedia/term/54212/warm-boot
Question 3:
Now please have a look on this attachment.
It says, "Secondly, in a bus request operation, the processor passes control of the system buses to the requesting device, which then handles all bus operations. The processor continues to execute instructions in the ISR or exception handler during interrupts."
If the processor passes control of all the buses to the requesting device then how could it keep on executing instructions in the ISR or exception handler during interrupts? Doesn't it need to regain the control of buses back to serve the interrupts?
Thank you for your help!