5-bit synchronous sequence recognizer design

In summary, the conversation is about designing a 5-bit sequence recognizer that can detect two specific sequences of bits (11001 and 10010) with overlapping capabilities. The output should be 00 when no sequence is detected, 01 when the first sequence is detected, and 10 when the second sequence is detected. The conversation also discusses the use of a state diagram or state table to design the circuit and suggests using a shift register and decoders to detect the sequences. There is also a mention of constructing two independent state machines to detect each pattern and combining the outputs. The conversation ends with a discussion about designing a Moore version of the circuit, adding an extra state and updating the state transitions to detect the sequences.
  • #1
CoolDude420
201
9

Homework Statement


I am trying to design a 5-bit sequence recognizer. The circuit has to detect two sequences of bits. The first sequence is 11001. The second is 10010. The output when no sequence should be 00. When the 1st input sequence is detected, the output should be 01. When the second sequence is detected, the output should be 10. Overlapping should also be detected. I'm designing a mealy type machine first.

Homework Equations

The Attempt at a Solution



The first step that we always do is draw a state diagram or state table whichever is easier. I chose to draw the state diagram first.

State Diagram:

10f5316a8d.jpg


A = No pattern has been detected yet
B = 1 has been detected.
C = 11 or 10 has been detected
D = 110 or 100 has been detected.
E = 1100 or 1000 has been detected.
F = 1101 or 1001 has been detected.

I am only meant to output 01 when the first sequence is detected(11001) and output 10 when the second sequence is detected(10010).
However as you can see with the bold bit numbers in the description for each state, if 10001(A>B>C>D>E>B) is detected, there will be an output of 01 there as well even though that is not a valid sequence.
Likewise with 11010(A>B>C>D>F>A), there will be an output of 10 even though its not a valid sequence.


I am quite confused as to how to fix this?
 
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  • #2
CoolDude420 said:
Overlapping should also be detected.
I presume that means that if one of the patterns occurs within a sliding 5-bit window that spans two adjacent packets, that is to constitute a match.
Sounds like using a shift register rather than a state machine would be a lot easier. Then build decoders to detect each of the patterns.

(When you get yourself into a box it's time to think outside the box.)
 
  • #3
You could construct two independent state machines, each detecting a specific pattern. Combine the outputs.
 
  • #4
Tom.G said:
I presume that means that if one of the patterns occurs within a sliding 5-bit window that spans two adjacent packets, that is to constitute a match.
Sounds like using a shift register rather than a state machine would be a lot easier. Then build decoders to detect each of the patterns.

(When you get yourself into a box it's time to think outside the box.)
lewando said:
You could construct two independent state machines, each detecting a specific pattern. Combine the outputs.

The specifications of the assignment say that it has to be one finite state machine to detect both the sequences(i.e one circuit block). Apologies for not including this in the initial post.
 
  • #5
You could recognize that you have 25 = 32 possible sequential input patterns. Assign each pattern to a state. You can then do the state transition interconnections.
 
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  • #6
lewando said:
You could recognize that you have 25 = 32 possible sequential input patterns. Assign each pattern to a state. You can then do the state transition interconnections.

I understand that. My issue is with the connections between the states themselves. Am I missing a few states or something in my diagram? Can you help me out with my diagram please? I don't see how I can fix it.
 
  • #7
You should not get too attached to a configuration, especially if it doesn't work. By the way, state E has no zero case exit path. Let me look at your diagram some more.
 
  • #8
lewando said:
You should not get too attached to a configuration, especially if it doesn't work. By the way, state E has no zero case exit path. Let me look at your diagram some more.

Here is an updated one. I completely changed it. Can you check this one instead please:
e7201e6280.jpg


Overlapping is allowed. I think this state diagram is correct.

EDIT: Theres a mistake with the C state. The line from C to D should actually be a line from C to C with 1/00 over it.
 
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  • #9
State C has two exit cases both zero-case.
 
  • #10
lewando said:
State C has two exit cases both zero-case.
Ah. Apologies for that. I have fixed it. New diagram:

7f2817d7dc.jpg


Is everything else okay?
 
  • #11
How did you test it?

Consider this sequence: 10010010. The first part works (10010 results in output=10), but the next three: 010 (when preceded by 10) should also produce output = 10, but you end up in state D with output = 00.
 
  • #12
lewando said:
How did you test it?

Consider this sequence: 10010010. The first part works (10010 results in output=10), but the next three: 010 (when preceded by 10) should also produce output = 10, but you end up in state D with output = 00.

Ah. I see. I think I have fixed it. I've tried some other sequences and they work fine. Is there anything else you can spot.
Here is the new version:

0061fe98df.jpg
 
  • #13
I think you got it! I checked it pretty extensively.
 
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  • #14
lewando said:
I think you got it! I checked it pretty extensively.

Awesome. Thank you very much. I really appreciate it. Apologies for my stupid mistakes.
 
  • #15
lewando said:
I think you got it! I checked it pretty extensively.

One last thing. I need to design a Moore version of this as well. I know there's two or three extra states but I can't seem to figure it out. Here is what I have so far:
139a3f4717.jpg


My issue is with the D,G,H area. Not exactly sure how I put in the extra new states?
 
  • #16
You had a Mealy transition path for 11001 of A -> B -> C-> E -> F -> .
Leave state A when you have detected pattern xxxx1.
Leave state B when you have detected pattern xxx11.
Leave state C when you have detected pattern xx110.
Leave state E when you have detected pattern x1100.
Leave state F when you have detected pattern 11001.

For a Moore, you will need to add an extra state: A -> B -> C-> E -> F -> F'
In state A you have detected pattern xxxxx.
In state B you have detected pattern xxxx1.
In state C you have detected pattern xxx11.
In state E you have detected pattern xx110.
In state F you have detected pattern x1100.
In state F' you have detected pattern 11001.

You had a Mealy transition path for 10010 of A -> B -> D-> G -> H ->.
Leave state A when you have detected pattern xxxx1.
Leave state B when you have detected pattern xxx10.
Leave state D when you have detected pattern xx100.
Leave state G when you have detected pattern x1001.
Leave state H when you have detected pattern 10010.

For a Moore, you will need to add an extra state: A -> B -> D-> G -> H -> H'
In state A you have detected pattern xxxxx.
In state B you have detected pattern xxxx1.
In state D you have detected pattern xxx10.
In state G you have detected pattern xx100.
In state H you have detected pattern x1001.
In state H' you have detected pattern 10010.

Work with that structure.
 
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  • #17
lewando said:
You had a Mealy transition path for 11001 of A -> B -> C-> E -> F -> .
Leave state A when you have detected pattern xxxx1.
Leave state B when you have detected pattern xxx11.
Leave state C when you have detected pattern xx110.
Leave state E when you have detected pattern x1100.
Leave state F when you have detected pattern 11001.

For a Moore, you will need to add an extra state: A -> B -> C-> E -> F -> F'
In state A you have detected pattern xxxxx.
In state B you have detected pattern xxxx1.
In state C you have detected pattern xxx11.
In state E you have detected pattern xx110.
In state F you have detected pattern x1100.
In state F' you have detected pattern 11001.

You had a Mealy transition path for 10010 of A -> B -> D-> G -> H ->.
Leave state A when you have detected pattern xxxx1.
Leave state B when you have detected pattern xxx10.
Leave state D when you have detected pattern xx100.
Leave state G when you have detected pattern x1001.
Leave state H when you have detected pattern 10010.

For a Moore, you will need to add an extra state: A -> B -> D-> G -> H -> H'
In state A you have detected pattern xxxxx.
In state B you have detected pattern xxxx1.
In state D you have detected pattern xxx10.
In state G you have detected pattern xx100.
In state H you have detected pattern x1001.
In state H' you have detected pattern 10010.

Work with that structure.

Ah. I see.
Is this correct?
51e3b02cfd.jpg
 
  • #18
You should be able to answer that question yourself by running a set of sequences through it. The sequences should be long enough to give complete coverage. 10 bits should be enough. The first 5 should be variable the last 5 one of your target patterns. So 64 sequences? Associated with each sequence is the expected responses. Additionally, it could help to organize your diagram to facilitate evaluation--instead of a cloud of bubbles, consider two distinct branches representing the two main "success paths"
 

FAQ: 5-bit synchronous sequence recognizer design

What is a 5-bit synchronous sequence recognizer design?

A 5-bit synchronous sequence recognizer design is a digital circuit that detects a specific sequence of 5 bits in a stream of data. It uses a clock signal to synchronize its operation with the data stream and outputs a signal when the desired sequence is detected.

How does a 5-bit synchronous sequence recognizer work?

A 5-bit synchronous sequence recognizer works by comparing the incoming bits with a predetermined sequence of bits. It uses a set of logic gates and flip-flops to store and compare the bits. When the sequence is detected, the circuit outputs a signal.

What are the applications of a 5-bit synchronous sequence recognizer?

A 5-bit synchronous sequence recognizer can be used in various applications such as error detection in data communication, pattern recognition, and control systems. It can also be used in security systems to detect specific codes or sequences.

What are the advantages of using a 5-bit synchronous sequence recognizer?

One of the main advantages of using a 5-bit synchronous sequence recognizer is its speed and reliability in detecting specific sequences. It can operate at high frequencies and can accurately detect the desired sequence without errors. It is also a relatively simple and cost-effective solution compared to other methods.

How can I design a 5-bit synchronous sequence recognizer?

Designing a 5-bit synchronous sequence recognizer requires a good understanding of digital logic and sequential circuits. The design process involves specifying the desired sequence, creating a truth table, and implementing the logic using logic gates and flip-flops. There are also software tools available that can assist in designing and simulating the circuit before implementation.

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