- #1
ensabah6
- 695
- 0
x86 is known to be register-starved, with only 8 GPR
AMD64 extends x86 8 GPR's to 16GPR. Many RISC such as PowerpC uses 32 GPR, which makes me wonder why AMD didn't extend the registers to 32 or even 64 total GPR
(same can be said for SSE, from 8 to 16, why not 32 or 64?) Itanium has over 100
AMD64 extends x86 8 GPR's to 16GPR. Many RISC such as PowerpC uses 32 GPR, which makes me wonder why AMD didn't extend the registers to 32 or even 64 total GPR
(same can be said for SSE, from 8 to 16, why not 32 or 64?) Itanium has over 100