Binary Encoding for 16 Bit Architecture

[ver_mathstats]

Homework Statement

We need to determine the binary encoding for five-stage pipeline with register banks, r0 to r3 is bank A, and r4 to r7 is bank B. It is a 16-bit architecture. Determine the largest offset that you can encode.

Relevant Equations

binary encoding, offset

In class we were given the example of a 32-bit architecture, so the opcode has 5 bits, register A had four bits, register B had four bits, the destination register had 4 bits and the offset was 15 bits, this was how it was done for "add" instruction. But when I was further reading about it online I saw that the opcode was a different amount of bits for a 32-bit architecture so are there several right answers to questions like this? And what are the different types of operand encodings I am a bit confused by this.

For a 16-bit architecture would it be 2 bits for the opcode, 4 bits for register A, 4 bits for register B, and then 4 bits for the destination register, and then it would be a maximum of 2 bits for the offset that I can encode? This is what I have in mind for the add instruction, am I on the right track with this?

Thank you.

 

[Tom.G]

How many bits are needed to count up to the highest numbered register?

 

[Mark44]

In class we were given the example of a 32-bit architecture, so the opcode has 5 bits, register A had four bits, register B had four bits, the destination register had 4 bits

It's hard to believe that there are only three registers in the 32-bit architecture your studying: reg A, reg B, and the destination register. In 32-bit MIPS there are 32 general purpose integer registers and the same number of floating point registers. In 32-bit ARM; e.g., ARMv7, there are 16 general purpose integer registers. An instruction needs to provide a sufficient number of bits to identify a register used as a source for an operation or the destination of that operation.

 

[pbuk]

It's hard to believe that there are only three registers in the 32-bit architecture your studying: reg A, reg B, and the destination register.

I think the OP means the instructions are encoded with four bits to identify each of the operand registers and the destination register. This implies 16 GP registers.

Homework Statement:: We need to determine the binary encoding for five-stage pipeline with register banks, r0 to r3 is bank A, and r4 to r7 is bank B. It is a 16-bit architecture. Determine the largest offset that you can encode.
...are there several right answers to questions like this?

Yes.

For a 16-bit architecture would it be 2 bits for the opcode,

I don't think a 2 bit opcode will work (hmmm could you get away with e.g. LW, SW, ADD and BEQ or do you need NAND as well? An interesting side-exercise.). Try searching for "16 bit RISC" for real world examples.

4 bits for register A, 4 bits for register B, and then 4 bits for the destination register,

There are 2 banks of 3 registers. How many bits to identify the bank (which I would assume applies to all registers in the instruction)? How many bits to identify each register within a bank? How many registers do you need to identify?

 

[ver_mathstats]

I think the OP means the instructions are encoded with four bits to identify each of the operand registers and the destination register. This implies 16 GP registers.

Yes that's what I mean.

Yes.

Okay thank you, this is the part that confused me a lot.

I don't think a 2 bit opcode will work (hmmm could you get away with e.g. LW, SW, ADD and BEQ or do you need NAND as well? An interesting side-exercise.). Try searching for "16 bit RISC" for real world examples.

Ah okay, I understand, 2 does not work for almost any of them.

There are 2 banks of 3 registers. How many bits to identify the bank (which I would assume applies to all registers in the instruction)? How many bits to identify each register within a bank? How many registers do you need to identify?

In class we were just shown examples where the opcode is given, then three registers. This was done for add, load, store, and jump and that was it for a total of 32 bits. I'm going to say based on looking at "16 bit RISC" we need a minimum of three bits for opcode and then three bits for each register. I'm a bit confused by what you mean with bits to identify the bank so sorry.

 

[Mark44]

In class we were just shown examples where the opcode is given, then three registers. This was done for add, load, store, and jump and that was it for a total of 32 bits. I'm going to say based on looking at "16 bit RISC" we need a minimum of three bits for opcode and then three bits for each register. I'm a bit confused by what you mean with bits to identify the bank so sorry.

For a 16-bit instruction, you need only one bit to identify the bank - 0 for bank 0, and 1 for bank 1.
First register; 3 bits (identifies registers 0 through 7
Second register: 3 bits (same as above)
Third register: 3 bits (same as above)

That leaves 6 bits remaining for the opcode, for a total of 64 different instructions.

 

[ver_mathstats]

For a 16-bit instruction, you need only one bit to identify the bank - 0 for bank 0, and 1 for bank 1.
First register; 3 bits (identifies registers 0 through 7
Second register: 3 bits (same as above)
Third register: 3 bits (same as above)

That leaves 6 bits remaining for the opcode, for a total of 64 different instructions.

Okay I see, we didn't use a bit for the bank in class which is why I was confused, so then the maximum offset we can encode is 3 bits if the opcode requires 3 bits minimum?

 

[Mark44]

Okay I see, we didn't use a bit for the bank in class which is why I was confused, so then the maximum offset we can encode is 3 bits if the opcode requires 3 bits minimum?

If you have only 3 bits for the opcode, you can have only 8 instructions. In the MIPS architecture, there are three different formats for instructions: R-format (mostly arithmetic-type instructions, in which three registers participate); I-format (loads and stores and some arithmetic instructions that involve constants); J-format (jumps and a few other instructions).

In whatever architecture you're working with, a load instruction or a store instruction requires only two registers, plus the offset where the value to be loaded or stored is located.

 

[ver_mathstats]

If you have only 3 bits for the opcode, you can have only 8 instructions. In the MIPS architecture, there are three different formats for instructions: R-format (mostly arithmetic-type instructions, in which three registers participate); I-format (loads and stores and some arithmetic instructions that involve constants); J-format (jumps and a few other instructions).

In whatever architecture you're working with, a load instruction or a store instruction requires only two registers, plus the offset where the value to be loaded or stored is located.

Thank you, mine only has 7 instructions that are implemented which I forgot to write so my apologies.

 

[pbuk]

For a 16-bit instruction, you need only one bit to identify the bank - 0 for bank 0, and 1 for bank 1.
First register; 3 bits (identifies registers 0 through 7
Second register: 3 bits (same as above)
Third register: 3 bits (same as above)

r0 to r3 is bank A, and r4 to r7 is bank B

I think this CPU only needs 2 bits per register as there are only 4 registers per bank, however there is more than one way of implementing banked registers.

Thank you, mine only has 7 instructions that are implemented which I forgot to write so my apologies.

Perhaps there are also some details on how the banked register addressing is implemented.

 

[Mark44]

I think this CPU only needs 2 bits per register as there are only 4 registers per bank,

I didn't remember that the OP had stated that there were four registers per bank. I was thinking that there were 16 registers in all.