- #1
jrive
- 58
- 1
In a lot of the literature out there, they make reference to the totem pole topology for driving Mosfets (as in an H-bridge) as shown in the figure attached. I for the life of me cannot understand how this is a good circuit. When the output from the PWM controller is high, the upper transistor is an emitter follower, so I expect to see Vout-vbe at the gate of the FET (assume no Rg for the sake of argument) -fine. However, when the PWM output is low, the upper transistor is off, but so is the bottom transistor (except perhaps while the charge stored in the FET's gate capacitance serves to provide the vbe for the bottom pnp transistor to turn on, briefly. After the cap discharges, though, the common node at the emitter of the two bipolar transistors is floating (isn't it?)...this is not a good thing, in my opinion. I would expect the high impedance input of the fet would then be susceptible to noise.
Can someone enlighten me please on what I'm missing with this topology?
Thanks!
Jorge
Can someone enlighten me please on what I'm missing with this topology?
Thanks!
Jorge