Built in Voltage of 3-Layer PN Junction

In summary, the conversation discusses finding the built-in voltage and fully depleted voltage for a PN junction with three layers - an N-doped region, a lightly P-doped region, and a P-doped region. The suggested approach is to integrate the carrier density and solve for the built-in voltage, but the presence of the lightly doped region complicates the analysis. It is suggested to treat the junction as a N+/P junction and determine the depletion region at zero bias to find the built-in voltage. If the depletion region extends into the P-doped region, it can be considered a N+/P+ junction. Further calculations may be needed to fully deplete the lightly doped region.
  • #1
Mr_Allod
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Homework Statement
A PN junction which consists of these 3 layers:

An N-doped region with ##N_D=5\times10^{18}cm^{-3}##

A lightly P-doped region with ##N_{Al}=1\times10^{15}cm^{-3}## with a thickness of ##2\mu m##

An P-doped region with ##N_A=3\times10^{18}cm^{-3}##
Find the built in voltage (##V_{bi}##) for the diode and the applied voltage at which the lightly P-doped region is fully depleted.
Relevant Equations
$$V_{bi} =\frac {kT}{q}\ln\left(\frac{N_A N_D}{n_i^2}\right)$$
For a normal PN junction I would try to find $V_{bi}$ by integrating the carrier density (eg. the electrons n) from one region to the other:
$$\int_{n_{p0}}^{n} \frac {dn}{n} = \frac {q}{kT}\int_{V_p}^{V_n} dV$$
Which would yield:
$$V_{bi}=V_n-V_p=\frac {kT}{q}\ln\left(\frac{n}{n_{po}}\right)=\frac {kT}{q}\ln\left(\frac{N_A N_D}{n_i^2}\right)$$

What has me confused is the presence of the 3rd dopant (lightly p-doped region). I'm not sure how I could alter the procedure to include it. I had the idea that I looking at it from the point of view of a PIN diode would be helpful but I'm not familiar with the analysis and I haven't been able to find much information on it. If someone could explain it to me I'd really appreciate it.
 
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  • #2
Mr_Allod said:
Homework Statement:: A PN junction which consists of these 3 layers:

An N-doped region with ##N_D=5\times10^{18}cm^{-3}##

A lightly P-doped region with ##N_{Al}=1\times10^{15}cm^{-3}## with a thickness of ##2\mu m##

An P-doped region with ##N_A=3\times10^{18}cm^{-3}##
Find the built in voltage (##V_{bi}##) for the diode and the applied voltage at which the lightly P-doped region is fully depleted.
Relevant Equations:: $$V_{bi} =\frac {kT}{q}\ln\left(\frac{N_A N_D}{n_i^2}\right)$$

For a normal PN junction I would try to find $V_{bi}$ by integrating the carrier density (eg. the electrons n) from one region to the other:
$$\int_{n_{p0}}^{n} \frac {dn}{n} = \frac {q}{kT}\int_{V_p}^{V_n} dV$$
Which would yield:
$$V_{bi}=V_n-V_p=\frac {kT}{q}\ln\left(\frac{n}{n_{po}}\right)=\frac {kT}{q}\ln\left(\frac{N_A N_D}{n_i^2}\right)$$

What has me confused is the presence of the 3rd dopant (lightly p-doped region). I'm not sure how I could alter the procedure to include it. I had the idea that I looking at it from the point of view of a PIN diode would be helpful but I'm not familiar with the analysis and I haven't been able to find much information on it. If someone could explain it to me I'd really appreciate it.
You don't need to do that. You do not have to alter the procedure. You just have to get clear which two regions constitute the actual junction and go from there.
 
  • #3
bob012345 said:
You don't need to do that. You do not have to alter the procedure. You just have to get clear which two regions constitute the actual junction and go from there.
My gut tells me it would be the two highly doped regions. But if that's the case what kind of effect would a lightly doped region (or even an intrinsic one) have on the properties of a PN junction?
 
  • #4
Mr_Allod said:
My gut tells me it would be the two highly doped regions. But if that's the case what kind of effect would a lightly doped region (or even an intrinsic one) have on the properties of a PN junction?
As I understand the problem as stated the device is an N+ layer, then a ##2\mu m## lightly doped P layer followed by the P+ layer. The lightly doped region is between the two heavily doped region. So the junction is N+ to P not P+. My intuition, which may be wrong, tells me the P+ region is essentially a contact unless the depletion depth extends into it so I think you can treat this problem as the limiting case. Test the properties of the N+/P junction. If the depletion region does not extend far enough to reach the P+ region you know what to do from there. As far as if the middle layer is intrinsic, that is used in amorphous silicon solar cells.FYI, here is an old link to a p-i-n junction but it assumes the N+ and P+ regions are equally doped.

http://superstrate.net/pv/cells/index.html
 
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  • #5
I see your point. I've done the calculation and at zero applied voltage the depletion layer is much less than 2 ##\mu m## in the N+/P case so you were right on the money.

Would I be right in thinking that if the depletion region reaches the P+ region (say under high enough reverse bias voltage), then I would consider the N+/P+ junction?

Also thank you for the link
 
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  • #6
Mr_Allod said:
I see your point. I've done the calculation and at zero applied voltage the depletion layer is much less than 2 $\mu m$ in the N+/P case so you were right on the money.

Would I be right in thinking that if the depletion region reaches the P+ region (say under high enough reverse bias voltage), then I would consider the N+/P+ junction?

Also thank you for the link
The original problem asks you to find the ##V_{bi}## and bias voltage to fully deplete the ##2 \mu m ## layer so that it just touches the P+ region. Only if you wanted to compute the depletion region beyond that into the P+ I think you would then treat the whole thing as a junction. I think you could also think of it as a N+/P+ junction if the thickness was thin enough to be fully depleted without an external bias. Frankly, I am not sure how exactly to do that myself yet which is why I think the problem is taking us to the edge. I think there is a hint in that link.

So what voltage do you get that will make the depletion region just touch the P+ region?
 
  • #7
bob012345 said:
The original problem asks you to find the ##V_{bi}## and bias voltage to fully deplete the ##2 \mu m ## layer so that it just touches the P+ region. Only if you wanted to compute the depletion region beyond that into the P+ I think you would then treat the whole thing as a junction. I think you could also think of it as a N+/P+ junction if the thickness was thin enough to be fully depleted without an external bias. Frankly, I am not sure how exactly to do that myself yet which is why I think the problem is taking us to the edge. I think there is a hint in that link.

So what voltage do you get that will make the depletion region just touch the P+ region?
So taking the junction to be N+/P I found ##V_{bi} \approx 0.82 V ##. Since ##x_p N_{Al} = x_n N_D## gives me that ##x_p = 5000 x_n## I made the assumption that the depletion width extends almost exclusively into the lightly doped region. Then the depletion width under bias is:
$$W = \sqrt {\frac {2\epsilon(V_{bi}-V_A)(N_D-N_{Al})}{qN_{Al}N_D}}$$
I made the approximation that ##N_D \gg N_{Al}## which simplified it to:
$$W = \sqrt {\frac {2\epsilon(V_{bi}-V_A)}{qN_{Al}}}$$

Rearranging to isolate ##V_A## (applied voltage) and setting ##W = 2\times 10^{-6} m## I found:
$$V_A = V_{bi} - \frac {qN_AW^2}{2\epsilon} = -2.8V$$

Also I used ##\epsilon_r = 10## so apologies for not mentioning that earlier.
 
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  • #8
Mr_Allod said:
So taking the junction to be N+/P I found ##V_{bi} \approx 0.82 V ##. Since ##x_p N_{Al} = x_n N_D## gives me that ##x_p = 5000 x_n## I made the assumption that the depletion width extends almost exclusively into the lightly doped region. Then the depletion width under bias is:
$$W = \sqrt {\frac {2\epsilon(V_{bi}-V_A)(N_D-N_{Al})}{qN_{Al}N_D}}$$
I made the approximation that ##N_D \gg N_{Al}## which simplified it to:
$$W = \sqrt {\frac {2\epsilon(V_{bi}-V_A)}{qN_{Al}}}$$

Rearranging to isolate ##V_A## (applied voltage) and setting ##W = 2\times 10^{-6} m## I found:
$$V_A = V_{bi} - \frac {qN_AW^2}{2\epsilon} = -2.8V$$

Also I used ##\epsilon_r = 10## so apologies for not mentioning that earlier.
That's what I did except I used ##k_s = 11.8## for silicon and got ##V_A = -2.24##.

I include a homework set I found from the University of California Berkeley that discusses pn junctions and compares it to a p-i-n junction since you brought that up. I think there is a minor typo in the definition of degeneracy in the solution set but you can ignore that.

https://www-inst.eecs.berkeley.edu//~ee130/sp13/homework/hw5.doc

https://www-inst.eecs.berkeley.edu//~ee130/sp13/homework/hw5soln.doc

Also, the book Physics of Semiconductor Devices by S.M. Sze discusses p-i-n diodes in detail.
 
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FAQ: Built in Voltage of 3-Layer PN Junction

What is the built-in voltage of a 3-layer PN junction?

The built-in voltage of a 3-layer PN junction is the voltage difference that exists between the P and N regions of the junction when it is not connected to an external power source. This voltage is caused by the diffusion of majority carriers across the junction, creating a depletion region with an electric field that opposes further diffusion.

How is the built-in voltage of a 3-layer PN junction calculated?

The built-in voltage of a 3-layer PN junction can be calculated using the following equation: Vbi = (kT/q) * ln(Na * Nd / ni^2), where k is the Boltzmann constant, T is the temperature in Kelvin, q is the elementary charge, Na and Nd are the doping concentrations of the P and N regions, and ni is the intrinsic carrier concentration.

What factors affect the built-in voltage of a 3-layer PN junction?

The built-in voltage of a 3-layer PN junction is affected by the doping concentrations of the P and N regions, the temperature, and the intrinsic carrier concentration. Higher doping concentrations and lower temperatures result in a higher built-in voltage, while a higher intrinsic carrier concentration leads to a lower built-in voltage.

How does the built-in voltage of a 3-layer PN junction impact its behavior?

The built-in voltage of a 3-layer PN junction plays a crucial role in its behavior. It determines the width of the depletion region, which affects the junction's capacitance and resistance. It also affects the junction's breakdown voltage and its ability to rectify current. Additionally, the built-in voltage is a key factor in determining the junction's forward and reverse bias characteristics.

Can the built-in voltage of a 3-layer PN junction be modified?

Yes, the built-in voltage of a 3-layer PN junction can be modified through the process of doping. By changing the doping concentrations of the P and N regions, the built-in voltage can be increased or decreased. This is a crucial aspect of designing and optimizing PN junctions for specific applications.

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