C++ or verilog or random process ?

In summary: I've taken a course on Intro to VHDL/Verilog in my second yr and I'm hoping that will give me a good foundation for C++.
  • #1
zaman999
6
0
C++ or verilog or random process ??

I'm currently in 3rd year of my undergrad in Electronics & Communication engg. For my 6th semester, I'm required to take 1 elective from the following-
-Data Structures with C++
-Random Process
-Digital System Design using Verilog
-Analog & Mixed mode VLSI design
-Satellite Communication

I don't know if Random process would be a good choice or not, from the rest, I'm interested equally in Digital design using Verilog, Data Structures using C++ but I need to make one choice.

I've had experience with Visual Basic in my high school which got me interested in programming but since then I've never got enough time to learn C++(or other lang) as I had to concentrate on 6 courses every semester.

I've taken a course on Intro to VHDL/Verilog in my 2nd yr.

I'm in a dilemma as to which one to go for from the first 3 choices as I get mixed opinions from my seniors. So could you give me a comparison of the 1st three in terms of how much they'll help me if I go for an MS in EE or an MS in EECS in the future?
Any suggestions to clear my confusion are welcome!

Regards,
Zaman
 
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  • #2


zaman999 said:
I'm currently in 3rd year of my undergrad in Electronics & Communication engg. For my 6th semester, I'm required to take 1 elective from the following-
-Data Structures with C++
-Random Process
-Digital System Design using Verilog
-Analog & Mixed mode VLSI design
-Satellite Communication

I don't know if Random process would be a good choice or not, from the rest, I'm interested equally in Digital design using Verilog, Data Structures using C++ but I need to make one choice.

I've had experience with Visual Basic in my high school which got me interested in programming but since then I've never got enough time to learn C++(or other lang) as I had to concentrate on 6 courses every semester.

I've taken a course on Intro to VHDL/Verilog in my 2nd yr.

I'm in a dilemma as to which one to go for from the first 3 choices as I get mixed opinions from my seniors. So could you give me a comparison of the 1st three in terms of how much they'll help me if I go for an MS in EE or an MS in EECS in the future?
Any suggestions to clear my confusion are welcome!

Regards,
Zaman

Is the C++ course an introduction to elementary data structures (classes, stacks, queues, linked-lists), or does it focus on some of the more advanced data structures for searching1, sorting2, graphs3?

You mentioned not having any time to learn C++. Does this mean you haven't had any exposure to it at all? If you cannot take an introductory course, you should spend some time on your own becoming familiar with it.

1Range Trees, kD-Trees, Quadtree, Hashing
2Selection Sort, Bubble Sort, Insertion Sort, Heapsort, Mergesort, Quicksort, Linear Time Sorts
3Searching (i.e., DFS and BFS), Shortest Paths (i.e., Dijkstra.s and Bellman-Ford algorithms)
 
  • #3


Dembadon said:
Is the C++ course an introduction to elementary data structures (classes, stacks, queues, linked-lists), or does it focus on some of the more advanced data structures for searching1, sorting2, graphs3?
My university scheme shows the units having stacks, queues, priority queues, skip lists & hashing, binary & search trees. We don't have the advanced data structures you mentioned.

You mentioned not having any time to learn C++. Does this mean you haven't had any exposure to it at all?
Oh, not really, we took an intro course on C in the first yr, what I meant was the system here doesn't really allow you to explore outside the curriculum.
 

FAQ: C++ or verilog or random process ?

1. What is the difference between C++ and Verilog?

C++ is a general-purpose programming language that is commonly used for developing software applications. It is primarily used for developing high-performance applications and systems programming. Verilog, on the other hand, is a hardware description language used for designing and modeling digital circuits. It is primarily used for designing and simulating hardware systems, such as integrated circuits and field-programmable gate arrays (FPGAs).

2. How are C++ and Verilog used in the field of engineering?

C++ is commonly used for developing software applications and systems, including engineering software such as computer-aided design (CAD) and computer-aided engineering (CAE) tools. Verilog is used for designing and simulating digital circuits, making it a valuable tool for engineers working on hardware systems.

3. Can C++ or Verilog be used for random process generation?

Yes, both C++ and Verilog have features that allow for the generation of random processes. In C++, the rand() function can be used to generate random numbers, while in Verilog, the $random function can be used for the same purpose.

4. Is C++ or Verilog more commonly used in the field of computer science?

C++ is more commonly used in the field of computer science, as it is a general-purpose programming language that can be used for a wide range of applications. Verilog, on the other hand, is primarily used in the field of electrical and computer engineering for designing and simulating hardware systems.

5. What are some common applications of random processes in computer science and engineering?

Random processes have various applications in computer science and engineering, including cryptography, simulation and modeling, data encryption, and random number generation for algorithms and games. They are also used for testing and debugging software systems and for generating realistic data for machine learning algorithms.

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