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atlbraves49
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I have a set of questions that won't be graded, but that my prof. wants us to look into/review. I've figured most of them out but the following have given me some issues. Any help would be appreciated. I don't mind getting the answers but a brief explanation would be best. Thanks!
1) The AVR RISC architecture is an 8bit architec. but has a 16bit fixed length instruction word. If the latter is transferred to the Instruction Register via a CPU internal bus, how many program memory accesses are necessary to retrieve a full instruction word?
(3, 4, 1, or 2)
2) If I/O peripheral devices are memory mapped, this means that:
a) I/O is performed using the same instruction as for reading or writing to the data memory
b) The instruction set implements two special instructions: IN and OUT.
c) I/O peripherals cannot be memory mapped because the architecture is Harvard
d) Peripherals have addresses in the program memory space
3) The architecture has a build in stack pointer. If one needs Two stacks, the second one could be implemented:
a) using one of the registers in the Data-Bank to point to the TOS of the second stack.
b) using the same stack pointer for both stacks
c)the second stack cannot be implemented
d) Using the program counter to point to the TOS of the second stack
4) If an architecture lacks an integer-multiply instruction, this could be implemented using a sequence of:
a) Shift and subtract
b) Shift and add
c) shift and rotate
d) increment and accumulate instructions
1) The AVR RISC architecture is an 8bit architec. but has a 16bit fixed length instruction word. If the latter is transferred to the Instruction Register via a CPU internal bus, how many program memory accesses are necessary to retrieve a full instruction word?
(3, 4, 1, or 2)
2) If I/O peripheral devices are memory mapped, this means that:
a) I/O is performed using the same instruction as for reading or writing to the data memory
b) The instruction set implements two special instructions: IN and OUT.
c) I/O peripherals cannot be memory mapped because the architecture is Harvard
d) Peripherals have addresses in the program memory space
3) The architecture has a build in stack pointer. If one needs Two stacks, the second one could be implemented:
a) using one of the registers in the Data-Bank to point to the TOS of the second stack.
b) using the same stack pointer for both stacks
c)the second stack cannot be implemented
d) Using the program counter to point to the TOS of the second stack
4) If an architecture lacks an integer-multiply instruction, this could be implemented using a sequence of:
a) Shift and subtract
b) Shift and add
c) shift and rotate
d) increment and accumulate instructions