Depletion depth in a PIN diode

In summary, the diode behaves as a diode with a high level of \pi layer doping, which is intentional. If the pi layer is not depleted, efficiency is reduced due to recombination.
  • #1
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Hi guys,

I'm trying to find a reliable formula for calculating the depletion depth in a PIN diode at a given voltage and knowing the doping of the layers. Does anyone have one? Formulae for the PN diode are common, but don't apply to the PIN directly as far as I can see.

I found a formula from here http://ece-www.colorado.edu/~bart/book/book/chapter4/pdf/ch4_3_6.pdf but I think the vaules that it gives are rather small considering the voltage. (?)

Cheers,
 
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  • #2
Welcome to PF! The penetration of the depletion zone into the highly doped n+ region is generally negligible compared to the width of the i layer, so in most cases you can ignore it and just use the i layer width.
 
  • #3
Thanks marcusl!

What do you do when you don't have an ideal I layer?

For example, I have some diodes here where the I layer isn't really undoped, but rather it has an unitentional doping (~1016 cm-3 (P type), compared with ~1018 cm-3 for the P and N layers).

The I layer is still << doped that the real P and N layers, but I'm interested in the diode's performace at low reverse bias voltages and until the reverse bias across the diode is sufficient to have fully depleted the I layer, I'm stuck not knowing how how the depleteion layer is growing. Hope that's explained well enough. Please could you shed any light in this instance?(PS. Having thought about it further and contemplated your post, I think the formula in the PDF is calculating how the depletion zone expends into N or P layer when the I layer is already fully depleted, which makes more sense. Thanks.)
 
  • #4
So you have a p-[tex]\pi[/tex]-n device instead of p-i-n. I think the biggest effect of the residual doping will be to reduce the effective charge lifetime, which can have a large effect on the diode's RF "on" properties. Due to recombination in the [tex]\pi[/tex] region, you'll need higher forward bias current to achieve the same on resistance and power handling.

Since you have actual devices, you should measure the performance (even if you calculate the performance, you'll still need to measure it for verification). Take a look at Joe White's book "Microwave Semiconductor Engineering," which has a very practical (vs. theoretical) orientation. He discusses how to measure all the parameters of interest, including lifetime.

Another change you'll see from the doped [tex]\pi[/tex] layer is a higher punch-through voltage, that is, the reverse bias required to deplete the i region. You determine it by measuring the junction capacitance at low frequency (1 MHz) vs. V_bias, and extrapolating past the soft "knee". Again, White discusses how to do it. You are correct to be worried about the growth of the depletion region with V_bias. Until you exceed V_PT, the device will have excess capacitance and excess RF leakage.

As you can see, the i layer affects both forward and reverse bias performance.
 
  • #5
Ok. Thanks very much. I'll look for that book. I've never heard them called P [tex]\pi[/tex] N before (just non-ideal PIN or PPN (& PNN))! Cheers.

FWIW, they're experimental diodes from another lab we're reverse biasing and using for X-ray spectroscopy rather than their original purpose. I'm trying to account for an increase in efficiency we see over and above what we expect when increasing the reverse bias voltage (not large enough reverse bias for avalanch multiplication though).

Thanks for your help.
 
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  • #6
Ah, you are interested in photodiodes and I assumed you were building RF switches. Regrettably I'm not familiar with photodiode literature. Glad I could be of some help all the same.
 
  • #7
Hello everybody!

A doping of 1016 cm-3 is intentional. Unintentional doping in Chokralsky silicon is rather about 1012 cm-3 (I mean: it was 20 years ago...)

I could imagine such an intention in a controlled-avalanche diode. Because electrons ionise more than holes do, having a bigger field at one electrode allows to amplify primary electrons but still quench the avalanche once the pulse is over. Useful for sure, but subtle. The same effect is obtained in particles detectors with wire chambers, where one electrode is a wire (high field) and the other a plate (lower field). Works only with one polarisation, and over a limited voltage range.

If your epitaxial region isn't fully depleted, it just means that your P[tex]\pi[/tex]N diode behaves as a [tex]\pi[/tex]N diode. All known formulas apply.
 
  • #8
I'd agree that the high level of [tex]\pi[/tex] layer doping was intentional, except the OP states it was unintentional. If this is a photodiode application, then the pi layer should be run depleted. Otherwise efficiency is reduced due to recombination, and the lower E field reduces the achieved drift velocity and slows down the response.

Maybe better to get a properly designed diode in the first place?
 
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  • #9
I have a question regarding the PIN diode: What would be the equilibrium condition in a pin diode without applying any external bias. would there be depletion region formed in intrinsic region.
 
  • #10
Holes diffuse from the p side a little way into the i region, and likewise electrons from the n side. There is still a depleted region at the center, but it is reduced from the i layer width. A small reverse bias will sweep these charges out and fully deplete the i layer width. This is known as the "punch-through" voltage.
 
  • #11
Thanks Marcus!
I am trying to solve the potential profile for a pin diode. I am considering the p-i and i-n junctions separately. What i want to know is that will this pin analysis can be done exactly as we do for pn junction but in pin case there won't be donors or acceptor ions in intrinsic region.
 
  • #12
Don't consider the two sides separately. In many practical devices the I region is actually very lightly doped instead of strictly intrinsic as mentioned earlier, so you have a p-pi-n or p-nu-n device instead of p-i-n. Accordingly the junction extends from, e.g., the p region into the nu layer and conventional p-n potential analysis can be used. This is covered in many textbooks including this one online:
http://ecee.colorado.edu/~bart/book/book/index.html"
 
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Related to Depletion depth in a PIN diode

1. What is the depletion depth in a PIN diode?

The depletion depth in a PIN diode refers to the region within the diode where the dopant concentration is depleted, creating a depletion layer. This layer acts as a barrier to the flow of current and allows the diode to function as a switch or rectifier.

2. How is the depletion depth in a PIN diode determined?

The depletion depth in a PIN diode is determined by the dopant concentration and the applied voltage. As the voltage is increased, the depletion layer expands, and the depletion depth increases. The dopant concentration also plays a role in determining the depletion depth, with higher concentrations resulting in a shallower depletion layer.

3. What is the significance of the depletion depth in a PIN diode?

The depletion depth in a PIN diode is crucial for its functionality. It allows the diode to act as a switch by controlling the flow of current. It also affects the diode's capacitance and resistance, making it an essential parameter for circuit design and optimization.

4. How does temperature affect the depletion depth in a PIN diode?

Temperature can affect the depletion depth in a PIN diode in two ways. Firstly, it can change the dopant concentration, altering the depletion depth. Secondly, temperature can affect the mobility of charge carriers, which can also impact the depletion depth. Generally, higher temperatures result in a shallower depletion depth.

5. Can the depletion depth in a PIN diode be adjusted?

Yes, the depletion depth in a PIN diode can be adjusted by changing the dopant concentration or the applied voltage. By increasing the dopant concentration, the depletion depth can be decreased, and vice versa. Similarly, adjusting the applied voltage can also alter the depletion depth. This flexibility allows for customization of PIN diodes for specific applications.

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