Designing a synchronous counter

In summary, the up counter has Ja=C'+B, Ka=BC, Jb=A+C, and Kb=1. The down counter has Ja=B'C, Ka=B'C' , Jb=1, and Kb=A+C' . The control input for the up and down counter is Ja=B'C, Ka=B'C' , and Jc=A'B. The control input for the down counter is Ja=B'C, Ka=B'C' , and Kc=A'B+AB'
  • #1
xtb789
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Hi everyone. There are 2 questions i cannot solve here. So i am hoping someone here can help me out. Here are questions:

(1) Design a synchronous counter using J-K flip flops which will count
through the sequence 0, 2, 4, 6, 8, 10, 12, 14, 0.

(2) Design a synchronous down counter using J-K flip flops which counts
backwards from 9 down to zero.
 
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  • #2
When designing a sync counter. You need to remember that the clock signal hits all the JK FF at once as opposed to a async counter (where the output of one FF is the clock for the other). Remember that all JK must be in toggle mode. We enable each J-K flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are "high." To do this we need AND Gates. Read http://www.allaboutcircuits.com/vol_4/chpt_11/3.html and then you may be able to build your counters. It also schematic diagrams for a few counters that you can reference.

One difference between the up and down counter, is the input that's fed into the AND Gate. For a up counter the Q input is fed into the AND Gate and for the down counter the Q(inverted) input is fed into the AND GAte.
 
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  • #3
i'm trying to find out how to design a synchronous up/down counter using JK Flip Flops. Counting up in the sequence 1,3,5,7,4,2 and down count 2,4,7,5,3,1. Also i would like to know how the control input will be connected to the counter?...
 
  • #4
Start by making a table of : Input and Present-State versus Next-State. This is called the state transition table.

Next you work out what values of J and K are required to make the above transitions. These truth tables (or k-maps) are called the flip-flop excitation tables (maps).

For optimal design don't restrict the JK flip-flops to only toggle function but use the following assignments to determine your flip-flop excitation.

Code:
PS NS   J K (comment)
0  0    0 X (no change or reset)
0  1    1 X (set or toggle)
1  0    X 1 (reset or toggle)
1  1    X 0 (no change or set)
 
  • #5
Up/down counter

Yeah...I've done all of that and got this.

Up counter>>...Ja=C'+B Ka=BC Jb=A+C Kb=1 Jc=AB Kc=A'
Down Counter>>...Ja=B'C Ka=B'C' Jb=1 Kb=A+C' Jc=A'B Kc=A'B+AB'

Now I'm stuck on how to merge the up and down counter with the control input....please help!
 

FAQ: Designing a synchronous counter

1. What is a synchronous counter?

A synchronous counter is a type of digital circuit that counts a sequence of binary numbers based on a clock signal. The output of a synchronous counter changes at the same time as the clock signal, making it synchronized with the clock.

2. How does a synchronous counter differ from an asynchronous counter?

A synchronous counter differs from an asynchronous counter in that it uses a common clock signal to trigger the change in its outputs, whereas an asynchronous counter uses individual inputs to trigger the change in each output.

3. What is the advantage of using a synchronous counter?

The advantage of using a synchronous counter is that it is more reliable and accurate than an asynchronous counter. The use of a common clock signal reduces the possibility of errors and ensures that all outputs are synchronized.

4. How is a synchronous counter designed?

A synchronous counter is typically designed using flip-flops and logic gates. The number of flip-flops used determines the maximum number of counts the counter can reach. The output of each flip-flop is connected to the input of the next flip-flop, creating a cascading effect.

5. What are some practical applications of synchronous counters?

Synchronous counters are commonly used in digital electronics, such as in digital clocks, frequency dividers, and digital frequency synthesizers. They are also used in data communication systems, signal processing, and controlling sequential operations in computer systems.

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