"Flow through" electrolytic capacitor

[artis]

For applications where the output has considerable ripple or spikes often just using electrolytic capacitors for DC smoothing is not enough because electrolytics themselves have some inductance and series ESR which is mostly the result of their inner structure (wire leads, pins, foil)

I was thinking , are there in existence such electrolytic capacitors which would have 4 leads, 2 on each side where one on each side connects to one foil and the other on each side to the other foil. The capacitor itself would then essentially be part of the wire as well as a capacitor, the current instead of flowing in and out of the leads and into the foil would just flow through the capacitor foil.

Think of it like a long transmission line situation compressed into a few cm of space whereby you have both wires/traces as well as distributed capacitance.
Wouldn't this minimize ESR and lower inductance?

Also the foil ends could be made similar to how Tesla thought to make their new tabless battery design whereby instead of leads the end of the whole foil is used for current transfer.?

Are there such capacitors or anything similar?

 

[anorlunda]

I'm not sure I understand your question. What benefit are you trying to achieve with a different structure?

 

[Averagesupernova]

I fail to see the advantage in this. Now instead of just AC ripple current in the capacitor leads you want the DC load current as well?

 

[tech99]

For applications where the output has considerable ripple or spikes often just using electrolytic capacitors for DC smoothing is not enough because electrolytics themselves have some inductance and series ESR which is mostly the result of their inner structure (wire leads, pins, foil)

I was thinking , are there in existence such electrolytic capacitors which would have 4 leads, 2 on each side where one on each side connects to one foil and the other on each side to the other foil. The capacitor itself would then essentially be part of the wire as well as a capacitor, the current instead of flowing in and out of the leads and into the foil would just flow through the capacitor foil.

Think of it like a long transmission line situation compressed into a few cm of space whereby you have both wires/traces as well as distributed capacitance.
Wouldn't this minimize ESR and lower inductance?

Also the foil ends could be made similar to how Tesla thought to make their new tabless battery design whereby instead of leads the end of the whole foil is used for current transfer.?

Are there such capacitors or anything similar?

I think you are asking for a feedthrough capacitor. They do have the desirable properties you suggest, but are not available as electrolytics as far as I know. https://passive-components.eu/feedthrough-capacitors-technology-and-applications/

 

[artis]

I'm not claiming there is/would be an advantage that is why I'm thinking about it out of curiosity.
Just imagine a parallel plate capacitor , the textbook example with straight plates, instead of each plate having a single lead attached on one side just imagine also a lead attached at the same plate on the opposite side.
Now you can use the plate as a "wire" but it is also a plate with the same capacitance. Now take the same concept and apply to an electrolytic cap.
Given many leads and the foil cross section it has more cross section than a wire so shouldn't get hot.
The idea is that attaching a cap in this way could
A) minimize ESR
B) lower inductance
C) Total capacitance shouldn't be affected because the plate separation and total area are the sameI thought about this because I was recently looking at a few year old thread of mine where I dealt with parasitic spikes on the DC output of a DIY smps I have. I am just now sorting out the problem and there are multiple phenomena that I will deal with but one (my original mistake) was that I have the secondary diode rectifier and then after that further down are the smoothing capacitor bank.
I soldered the DC output on the traces between the bridge rectifier diodes and the capacitors although I suspect that attaching the DC output after the capacitor bank would give a less "noisy" output.
I think the ripple on the traces between diodes and caps is more than on the traces after the caps.
But I cannot say for certain yet this is where I will come back to in the following months and probably reply in that old thread of mine because it had some good suggestions there.

 

[Averagesupernova]

@artis has is occurred to you how surface mount capacitors are built? We are getting the capacitor plates as close as possible to the PC board and are not rerouting signals (DC or otherwise) off the board, through the capacitor and back onto the board.
-
Maybe I misunderstand you, but can I assume the idea is centered around DC power rails? Reducing the ripple as much as possible while keeping the series resistance as low as possible?

 

[DaveE]

I don't think they would be very popular since they are harder to deal with mechanically. I have seen some, as I recall, where the case was a terminal with a stud in the bottom. But the electronic component industry tends toward standardization (in a general sense) for high volume and lower production costs.

Also, I think the gains aren't really significant. For example, in the normal tab configuration below, let's consider a capacitor with length L. The electrons that take the shortest path travel length 0. The electrons that take the long path travel length 2L. So, on average, they travel length L. In your configuration, they would all travel length L.

The internal construction to allow radial spreading of the electrons (without moving in a spiral) is much more important, I think. In very low ESR designs the foils are offset and connected across with tabs folded over to achieve this.

 

[Windadct]

Ah, after a second read I see what you were proposing. The 4 wire cap would have the load current flowing through it ?

Consider this - we use Caps to filter voltage, and the current of the application (load) is not part of the problem. The non-desirable parasitic characteristic impact the capacitors response to voltage changes. Basically the ESR in in series with the capacitor no matter how you hook it up. In fact having the "load" current flowing through the same terminals may actually make matters worse.

It is pretty common to just include a second, small signal cap in parallel to the larger cap.

 

[artis]

Well now I'm not sure whether some of you understood what I said, @Windadct just take the picture @DaveE posted and imagine the tabs go "out" through the cap also in the other direction sort of like wires just passing through the capacitor and at the same time they are attached to the foils also.
I hope I have now made it as clear as possible without a detailed picture or schematic.

Essentially like having a transmission line of very short length (the length of a straight trace couple of cm long) while having the capacitance of a long transmission line or just an electrolytic capacitor.
The idea is to actually use the foil itself as the tab, just like Tesla did with their "tabless" batteries. In this way you minimize inductance and maximize current capability, have the lowest possible resistance etc.
Not sure whether this has been done before with caps , just a thought.

 

[DaveE]

Oh, yes I also see your point now. I think my previous comment still applies. I'm not convinced you get much advantage, especially with electrolytics which have inherently high esr. Many of these sorts of discussions apply more to high energy discharge capacitors (almost exclusively film or oil types) like in radar PFNs, flash lamps, rail guns, and such.

One problem is that in filtering applications the load current is much greater than the ac shunt current through the capacitor. So, you would need big conductors in the load path. It just doesn't seem advantageous to build those into the capacitor enclosure. The normal configuration of parallel buss bars with caps directly mounted across is hard to beat. Again, the capacitor industry wants to build parts that everyone can use, to increase volume and lower costs.

 

[DaveE]

Not sure whether this has been done before with caps

As @tech99 said, this is a standard RF feedthrough capacitor configuration. Those are all about emi filtering, not high power though. You'd never see an electrolytic cap there, they just aren't good capacitors, except for their ability to store energy with high density.

 

[Baluncore]

Wouldn't this minimize ESR and lower inductance?

To reduce the inductance of a foil electrolytic, put a smaller multilayer ceramic ( 0u1 skycap ) in parallel. The multilayer cap will handle the HF components while the electrolytic will handle the LF components.
The electrolytic will run cooler as charge has a longer time to flow, so current is less, as is W=I²⋅R_s , with the ripple current squared advantage.

 

[tech99]

As a matter of interest about putting capacitors in parallel, if each of them possesses a series resonance to ground, then between these two resonant frequencies there will always be a parallel resonance, where impedance to ground is high.

 

[Windadct]

OK - in a way yes, it is very expensive we were doing this with MetalFIlm caps for SiC systems, trying to switch > 25 kHz we ran into resonance, but ALSO the series inductance causes EMI and V overshoot on turn off... anyway...

We had the foil brought out and run to a similar sandwich DC link. But the big issue here was inductance, we had it down to about 1-2 nH, necessary when switching a few hundred amps. ESR was basically internal - the foil and heated the cap internally. So this became a lifetime discussion, balancing allowable ripple, total capacitance, heating and the ever important $$$.

 

[artis]

OK - in a way yes, it is very expensive we were doing this with MetalFIlm caps for SiC systems,

Some sort of compliance testing?

 

[Windadct]

Some sort of compliance testing?

No - actual development of higher power systems ( >100KW) - the DC link and commutation loop inductance are critical. Using a flex foil circuit allows for a sandwich construction. Managing this inductance is critical due to the SiC speed.