- #1
masterchiefo
- 212
- 2
Homework Statement
VHDL code:
http://i.imgur.com/UZrK1ky.png
Homework Equations
B2 = B7 * A1
B3 = (B9 * B2) + (B1(1) * /B1(0) * /A1
B6 = B9 + /A1
B8 = B2 + (B9 * /A1) + (/B5 * (A1 + B7))
If Clock = 1 and rising edge on A2 then we reset B4, B5, B7 to 0.
Else
B4 = B3 = (B9 * B2) + (B1(1) * /B1(0) * /A1
B5 = B6 = B9 + /A1
B7 = B8 = (B2 + (B9 * /A1) + (/B5 * (A1 + B7)))
then this part is confusing me.
end process;
B1 <= B4 & B5 & B7; //What does this mean?
B9 <= '1' when B4 = '0' and B5 = '1' else '0'; //B9 will equal 1 only if B4 and B5 is = to 1 else B9 = 0.
with B1 select //Do not understand this part what does B1 select mean?
A3 <=
'0' when "000" | "111", //when what is 000 or 111?
'1' when others;
end architecture a1;
The Attempt at a Solution
N/A