- #1
hoheiho
- 47
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Hi, i am trying to do a bit shift in systemverilog and compare the bit. For example:
i give a input A=011. Then the input will compare with another digital that i have already setup in fsm like 010. Now it will do the compare,
0 to 0---> bitmatch=1
1 to 1 ---> bitmatch=1
1 to 0 ---> bitmatch=0
How can i do the bit shift in here? i did some research in google it say i can use >> for right shift but it will gives a 0 bit on the other side. what i want is just compare it bit by bit and go to next stage.
Thanks for the help
i give a input A=011. Then the input will compare with another digital that i have already setup in fsm like 010. Now it will do the compare,
0 to 0---> bitmatch=1
1 to 1 ---> bitmatch=1
1 to 0 ---> bitmatch=0
How can i do the bit shift in here? i did some research in google it say i can use >> for right shift but it will gives a 0 bit on the other side. what i want is just compare it bit by bit and go to next stage.
Thanks for the help
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