- #1
Weaver
- 70
- 6
- Homework Statement
- Complete timing signal from VHDL and identify what the circuit is used for (see picture below)
- Relevant Equations
- N/A
I have attempted to sketch the timing and got the following graph
From reading the VHDL code my understanding is io each rising edge clock tick the system will carry out one of the following (choosing based on priority):
- reset if Clear_L is high
- load in a value if Clear_D is high
- UP count if Up is high
- Down count if nothing else
Points of interest are:
- IQ rolls over to 128 when 0-1 happens (I believe that's how unsigned works in VHDL)
- Q lags one behind IQ as with VHDL will simultaneous carry out all lexical blocks of code, meaning the check for UP will occur at the same time Q is assigned to IQ so it won't capture the changed value
EDIT: It would roll over to 256 not 128 in the graph as IQ is 8 bits, (I mistakenly read it as 7 bits)
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