Implement a function with 2-input NAND gates

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In summary, implementing a function with 2-input NAND gates involves using a logic gate that produces a low output only when both of its inputs are high. This type of gate can be used to create any logical function, making it a versatile and commonly used component in digital circuits. By connecting multiple NAND gates together, complex functions can be achieved, making it an essential tool in digital logic design.
  • #1
alfonwob
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Hello people!

I've just done a K-Map and gotten both the SOP and POS, but have a problem with this function:

f = acd + cab + dab + cdab + abcd ,
f = (a+b+c+d) * (b+c+d) * (b+c+d) * (a+b) * (a+c) * (a+d)

and got to implement it only using NAND gates with 2 inputs. Notice the underline is the negated variable.

Thank you so much in advance.
 
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  • #2
alfonwob said:
Hello people!

I've just done a K-Map and gotten both the SOP and POS, but have a problem with this function:

f = acd + cab + dab + cdab + abcd ,
f = (a+b+c+d) * (b+c+d) * (b+c+d) * (a+b) * (a+c) * (a+d)

and got to implement it only using NAND gates with 2 inputs. Notice the underline is the negated variable.

Thank you so much in advance.

Welcome to the PF.

What did you get from your K-map? Do you know how to make an OR gate from NAND gates to implement your SOP solution?
 
  • #3
Hi, thanks for your answer. I got (1 / 1 / 0 / 0 ... 0 / 1 / 0 / 0 ... 1 / 0 / 1 / 0 ... 0 / 1 / 0 / 0 ) I know how yo do an OR gate from 2 variables, not for more.

Image last number in right bottom is 0, not 1.
 

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  • #4
alfonwob said:
Hi, thanks for your answer. I got (1 / 1 / 0 / 0 ... 0 / 1 / 0 / 0 ... 1 / 0 / 1 / 0 ... 0 / 1 / 0 / 0 ) I know how yo do an OR gate from 2 variables, not for more.

Image last number in right bottom is 0, not 1.

To build a wider OR gate, you just make a tree of 2-input OR gates...

http://www.electronics-tutorials.ws/logic/log11.gif
log11.gif
 
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  • #5
berkeman said:
To build a wider OR gate, you just make a tree of 2-input OR gates...

http://www.electronics-tutorials.ws/logic/log11.gif
log11.gif

Thanks again for helping me.
Ok I understand the image you've attached but I have just to use NAND gates with 2 inputs.

I upload a picture where I show you the step I'm stuck in, just in the the part when I have to add both terms.
 

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  • #6
You need to include the inverters as part of each OR stage. You show the final stage without those inversions...
 
  • #7
But I only have NAND gates with 2 inputs. It's a rule from the exercise.
 
  • #8
alfonwob said:
But I only have NAND gates with 2 inputs. It's a rule from the exercise.

You already show in that drawing how to use a 2-input NAND to make a NOT gate... That's how you got your first 2 NOR gate equivalents...
 

Related to Implement a function with 2-input NAND gates

1. What is a NAND gate?

A NAND gate is a type of logic gate that performs a logical operation called "NOT-AND". It has two or more inputs and one output. The output of a NAND gate is only 0 (false) when all of the inputs are 1 (true), otherwise, the output is 1 (true).

2. Why use only NAND gates for this function?

NAND gates are considered universal gates, which means that any other type of logic gate can be constructed using only NAND gates. This makes them a convenient choice for implementing complex logic functions.

3. How do you implement a function with 2-input NAND gates?

To implement a function with 2-input NAND gates, you will need to use a combination of these gates in a specific configuration. This can be done by first writing the truth table for the desired function, and then using Boolean algebra to simplify the expression and determine the necessary configuration of NAND gates.

4. What are the advantages of using NAND gates for logic functions?

One advantage of using NAND gates is that they are relatively simple to implement and require fewer components compared to other logic gates. They also have a fast response time, making them suitable for high-speed applications.

5. Are there any limitations to using NAND gates for logic functions?

The main limitation of using NAND gates is that they can only perform the NOT-AND operation, which means that more complex logic functions may require a larger number of gates and can become more complex to implement. Additionally, NAND gates have a limited number of inputs, so larger functions may require multiple levels of NAND gates.

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