Is 70ps a Normal Propagation Delay for a 90nm Full Adder?

In summary, the conversation discusses designing a full adder for a 16-bit ALU and obtaining a propagation delay of 70ps for the AND mode in a low voltage 90nm process. The typical propagation delay for a full adder is in the hundreds of nanoseconds, with individual operations taking around 40-50 nanoseconds. However, gate delays can vary based on factors such as input capacitance and supply voltage. The speaker also expresses surprise at the idea of individual operations taking 45-50 nanoseconds, as CPUs in 2008 were operating at more than 20 MHz.
  • #1
nmaganzini
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Hi guys,

I was just wondering, I'm designing a full adder for a bitslice of a 16 bit ALU.

I have SPICED my design and I am getting a propagation delay for the AND mode between the two bits of about 70ps.

I'm working in a low voltage 90nm process.

Am I in the right ballpark in terms of propagation delay? or am I absurdly off? What is a typical propagation delay for a full adder (order of magnitude).

Thanks
 
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  • #2
If I recall correctly (it's been a while, so I might be off), the delay for the entire adder circuit is usually in hundreds of nanoseconds, and individual operations (AND and XOR) take about 40 to 50 nanoseconds each (with 45nm technology).

But as you might know already, gate delays depend on a number of factors such as the input capacitance, threshold and supply voltages etc. So there might be nothing wrong with the numbers that you have obtained.
 
  • #3
45-50 nanoseconds for individual operations would surprise me. Even with an extremely long pipeline a CPU has to get those operations done within a cycle, and in 2008 they certainly had more than 20 MHz.
 

FAQ: Is 70ps a Normal Propagation Delay for a 90nm Full Adder?

What is a typical full adder gate delay?

A typical full adder gate delay refers to the amount of time it takes for a full adder gate to process and output a result. The delay is measured in nanoseconds (ns) and is dependent on various factors such as the type of technology used and the complexity of the circuit.

Why is the full adder gate delay important?

The full adder gate delay is important because it affects the overall performance and speed of a circuit. A longer delay means it takes longer for the circuit to produce an output, which can impact the functionality of the circuit in real-time applications. Therefore, it is important for scientists and engineers to understand and minimize the delay in order to optimize circuit efficiency.

How is the full adder gate delay calculated?

The full adder gate delay is calculated by measuring the time it takes for the output to change after a change in the input. This is typically done by using a frequency generator to produce a series of input signals and measuring the corresponding output signals with an oscilloscope. The delay is then calculated by dividing the time difference between the input and output signals by the number of stages in the circuit.

What factors can affect the full adder gate delay?

The full adder gate delay can be affected by various factors, including the type of technology used (e.g. CMOS, TTL), the operating voltage and temperature, the size and complexity of the circuit, and the load capacitance. Additionally, external factors such as noise and interference can also impact the delay.

How can the full adder gate delay be reduced?

There are several ways to reduce the full adder gate delay, such as using faster switching transistors, optimizing the layout of the circuit, and reducing the number of stages in the circuit. Additionally, techniques such as pipelining and parallel processing can also be used to improve the speed and reduce the delay of a circuit.

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