JK flip flop master slave - Master remembers?

In summary, the clock pulse changes the value of the JK master-slave flip flop, but the SR (slave reset) for the master is *gated* by the constant output from the slave.
  • #1
DrOnline
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NB: Got a bit wordy, highlighted question in red.

Homework Statement


Just a picture of what we're dealing with.

I'm given a clock pulse, J and K inputs, and asked to describe the JK master-slave flip flop output.

Homework Equations



J K Q(t+1)
0 0 Q(t) No change
0 1 0 reset
1 0 1 set
1 1 Q'(t) Complement

The Attempt at a Solution



I understand:

Clock = 1 -> Master value can be modified by changes to J and/or K
Clock = 0 -> Value of Slave is set to that of Master

4TavN.jpg


Sorry for the drawing, I hope it is sufficient. During the positive clock phase I called 2, there is a brief blip in the J.

J & K are both 1, so I complement the Master value. it is now 1.

Now here is where I get uncertain. As I understand it, ANY change in J and/or K, even if there are 1000 changes, during a positive clock phase, will be reflected in the master. So only the FINAL value, once the clock drops from 1 to 0, in the master, "sticks".

So I say: that blip in J, well it drops quickly, during a positive clock phase, and so that leaves us with J = 0, K = 1, which is reset, so I drop the Master to 0 again.

However, this professor:



(skip to 4:10)

he's got an image from a book that says: "...something tricky about the master-slave, it's called the "one's catcher", it remembers any activity on the J or K while the clock is high. The J went high, then it went low, but it remembers".

It remembers? Can somebody explain how it remembers?
 
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  • #2
You have to take a look at the internal circuit, video at 1:30.

The SR for the master is *gated* by the constant output from the slave. If the slave has Q=1, setting J=1 on the master is ignored. Likewise if the slave has Q=0, setting K=1 on the master is ignored. In other words, if slave Q=1 you can only reset the master bit and if slave Q=0 you can only set the master bit with no way to take it back.

I suppose this turns into 'remembering ones', which may be a good mnemonic device once it's confirmed, but it doesn't teach anything :-/
 
  • #3
Oh yeah. I see the Q and Q' values from the slave are wired back into the input gates of the master. That has some implications I have to take into account.

I agree with your statement on remembering ones. I can't accept that without understanding it, so thanks a lot for your help! Gonna take another look at this task tomorrow and make some adjustments. ;)
 

FAQ: JK flip flop master slave - Master remembers?

1. How does a JK flip flop master slave work?

A JK flip flop master slave is a type of sequential logic circuit that can store one bit of data. It consists of two flip flops connected in a series, with the output of one flip flop connected to the input of the other. The master flip flop is used to capture the input data, while the slave flip flop is used to store the data and output it.

2. What is the purpose of the master and slave flip flops in a JK flip flop master slave?

The master and slave flip flops work together to improve the performance and reliability of the JK flip flop. The master flip flop is used to capture the input data, while the slave flip flop is used to store the data and output it. This allows the circuit to have more stable outputs and avoid any glitches or unwanted changes in the output.

3. How does the master flip flop remember the input data in a JK flip flop master slave?

The master flip flop remembers the input data by using the clock signal to capture the data and hold it in its internal state. This prevents any changes in the input data from affecting the output, as the master flip flop will only capture the data when the clock signal is high.

4. What is the advantage of using a JK flip flop master slave over a basic JK flip flop?

The JK flip flop master slave has several advantages over a basic JK flip flop, including improved stability and reliability of the output, reduced risk of glitches, and the ability to store the data for a longer period of time. It also allows for more complex logic circuits to be built using multiple JK flip flop master slaves.

5. How is the data output of a JK flip flop master slave affected by the clock signal?

The data output of a JK flip flop master slave is only affected by the clock signal during the rising edge of the clock. This means that the data will only be captured and stored in the slave flip flop when the clock signal transitions from low to high. This helps to prevent any unwanted changes in the output due to fluctuations in the clock signal.

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