Minimization with a binary to seven segment decoder in Verilog

[berkeman]

Why did you label your 7-seg like that? Isn't it suppose to be like http://www.engr.colostate.edu/~dga/mechatronics/figures/6-34.gif ?

Yikes, you might be right. I looked in my HP Opto catalog and just went from there, but I may have gone a bit too quickly. I'm at home now without the HP catalog, and a quick google gave me the same a-g ordering as you posted

http://www.ibiblio.org/kuphaldt/socratic/output/proj_ctr.pdf

Sorry if I confused anybody. I wish I could claim that I was just testing y'all again...but then again, if I were testing folks, you passed the test ranger!

 

[Maxwell]

Hey guys, sorry it took so long for me to reply. I've been finishing up some other work.

It turns out the problem was solved by using the product of sums instead of the sum of products for the active low device. The device works in simulation now, and I'll be testing it on a FPGA later.

Thank you both so much, berkeman and ranger! You were both very helpful and patient and I appreciate it very much.