MOSFET channel length modulation

[McKendrigo]

Hi there, I'm a bit beffudled by some of the workings of a MOSFET transistor.

First of all, in the saturation region of operation, I understand that the inversion channel is "pinched off" as it approaches the drain. In other words the inversion channel thickness tapers off as it approaches the drain. Because of this, and I quote from a textbook the channel's "resistance becomes larger with increasing drain voltage, resulting in a lower rate of increase in drain current". Indeed, in a plot of drain current vs. drain voltage, the current is seen to level off.

This seems fine to me, but when I read about the channel length modulation I read that if we increase the drain voltage we shorten the length of the channel by "pinching off" more and more of it, and "Because resistance is proportional to length, shortening the channel decreases its resistance, causing an increase in current with increase in drain bias for a MOSFET operating in saturation."

This seems counter intuitive to me: if the channel has been pinched off, how can carriers readily flow between the source and drain? How can increasing the drain voltage cause the channel resistance to both decrease and increase? I can grasp that the resistance of the channel decreases simply because the resistance is proportional to how much length of channel you have...but if the channel no longer bridges between source and drain how come that doesn't mean that the resistance between source and drain is not "infinite"?

I hope my question is clear...I may be rambling a bit here ;)

 

[jsgruszynski]

Hi there, I'm a bit beffudled by some of the workings of a MOSFET transistor.

First of all, in the saturation region of operation, I understand that the inversion channel is "pinched off" as it approaches the drain. In other words the inversion channel thickness tapers off as it approaches the drain. Because of this, and I quote from a textbook the channel's "resistance becomes larger with increasing drain voltage, resulting in a lower rate of increase in drain current". Indeed, in a plot of drain current vs. drain voltage, the current is seen to level off.

This seems fine to me, but when I read about the channel length modulation I read that if we increase the drain voltage we shorten the length of the channel by "pinching off" more and more of it, and "Because resistance is proportional to length, shortening the channel decreases its resistance, causing an increase in current with increase in drain bias for a MOSFET operating in saturation."

This seems counter intuitive to me: if the channel has been pinched off, how can carriers readily flow between the source and drain? How can increasing the drain voltage cause the channel resistance to both decrease and increase? I can grasp that the resistance of the channel decreases simply because the resistance is proportional to how much length of channel you have...but if the channel no longer bridges between source and drain how come that doesn't mean that the resistance between source and drain is not "infinite"?

I hope my question is clear...I may be rambling a bit here ;)

First possible source of confusion: the separateness of depletion and inversion modes.

The former is due to Vgs bias while the latter is due to Vds bias once you've achieved depletion. That may be where the confusion is coming from. This also gets into how the various MOS models in SPICE work. First you calculate the depletion effect vertically and then calculate the IV of inversion horizontally.

Basically, you form a channel initially by repelling carriers in the channel - that's depletion. At that point you only have ionic charge from dopants in the channel, so you have a potential channel for Ids but depletion itself doesn't result an Ids current to flow until you have a Vds bias. So Vgs and Vds bias are partially orthogonal in effect at a device level.

The second possible confusion: the difference between MOS channel depletion vs. a PN junction depletion layer.

Each has a similar name but there are actually different phenomena. Both involve depleting carriers from ionic semiconductor dopant atoms but a PN junction means you have two different polarities of depletion. There is a reverse-biased PN junction depletion layer at the channel-drain. The bias across this junction causes the immobile dopant ions to create an E-field across the junction aligned opposite to the Ids current - which is attractive to the inversion carriers in the depleted MOS channel so they get swept out once they reach this depletion layer. Once that happens, channel transit is over and the carriers are Ids current.

The third possible confusion: what pinch-off really means.

Pinched-off doesn't actually mean no current flows. It's probably a poorly chosen name but it's what it's called. What you are "pinching-off" is the prior scheme of monotonic increase in Ids with Vds (linear or square-law). Pinch-off point defines when the inverted channel (rather than depleted channel), which is the depleted channel being progressively filled with carriers as Vds increases, stops getting longer because it hits the drain PN depletion layer - thus limiting Ids. The carrier volume per unit time flowing through the channel can't get any bigger. Pinch-off is where the Ids-vs-Vds slope flattens out as increasing Vds stops increasing Ids.

Think of it as an empty pipe that fills with water as water pressure is increased. The water pipe is created from "thin air" by gate bias electrostatics. Initially the water gushes out into the pipe near the source, fills that side first and trickles out at the end. Presuming the water volume increases with pressure, you progressively fill the pipe more completely. Until the entire pipe diameter and length is filled - at that point the volume-rate of water saturates and flattens with more pressure. This is pinch-off. Or saturation.

At pinch-off you are still conducting carriers but now you have a situation akin to a bipolar transistor at maximum injection with minority carrier base transit to the base-collector depletion layer - once the injected carriers in the channel hit the channel-drain PN depletion layer they are swept out by the high reverse field and become drain current "instantly" and the current no longer changes with drain bias. In a bipolar this limit is due to maxing out minority carrier injection level so that collector current stops increasing with more Vce. And it's why the output current vs output voltage curves look pretty much the same with both technologies. Of course, saturation in a bipolar isn't saturation in a MOSFET, by accident of techno-linguistic history.

The difference, however, is that there are no true majority carriers in the MOS depletion channel any more (due to MOS electrostatic depletion caused by gate bias) so the channel carriers (which would be strictly minority carriers in the non-depleted or accumulated channel) look effectively like majority carriers in terms of recombination - there simply is no recombination because the "real" majority carriers are gone. This is exactly the opposite of a bipolar base region where the presence of majority carriers with injected minority carriers results in exponential decay of minority carriers with distance into the base from the base-emitter depletion layer. But it's similar in that the "backstop" for active device carriers is a reverse biased PN depletion layer.

Once you get how this works, then there are several causes of channel length modulation that result in effective channel length being shorter (or longer) than the diffusion/implant defined length.

The first order channel length modulation is due to the width modulation of the depletion layer of the drain-channel PN junction. If you intrude the PN depletion layer into the MOS depletion channel, you see pinch-off effects sooner. Naturally Vds bias changes the drain-channel PN junction bias altering the depletion width. This is akin to how bipolar base-collection bias modulates base width, especially due to the generally lower doping (and thus wider and more bias-sensitive width) of the BC PN junction.

So you get this channel length modulation normally at the higher end of operating Vds, which is why real MOSFET saturation region curves aren't actually flat. You are getting channel length reductions due to intrusion of the depletion layers at higher Vds bias, so you effectively increases the Ids output drive by shifting the physical point of pinch-off contact in the channel.

This modulation can become significantly amplified by the use of LDD, DDD and other hot carrier injection (HCI) amelioration drain design techniques. The reason is exactly the same except that now the depletion layer has been purposely made wider by using lower doping (and thus incidentally resulting in greater channel length modulation) in order to reduce the depletion layer E-field so that hot carrier generation is reduced. The other half of this amelioration is Vdd reductions from 5V to 3.3V or lower. It's this channel modulation that causes the flat parts of Id-vs-Vds curves of small geometry MOSFETs (which need LDDs, et al., due to HCI effects) to bend up in slope more radically than with large geometry devices. At least until you start having drain-source breakdown which happens to look similar.

A second order channel modulation source is, once you get HCI for a while, you start to form built-in trapped charge in the form of interface states and bulk traps formed by HCI currents into the oxide and resultant damage. This essentially pre-biases the transistor channel depletion effect (shifts the surface potential, $$\phi$$_s, exactly like a floating gate NVM like Flash) exactly where the HCI occurs which is just above the max E-field area of the drain-channel depletion layer.

This effectively shortens the channel length in the case of a PMOS device and lengthens it in the case of a NMOS device which is why you get the device-type-dependent shifts in Vt, Gm and Id parameters as a result of HCI damage. You've basically changed the depletion channel length but the inversion channel creation happens the same way but hits pinch-out earlier or later, depending.

And a factoid related to this: NAND flash memory explicitly relies on HCI currents for write phase programming so you get this kind of damage from "normal" write-erase cycle operation. This is what causes endurance which is a finite number of write-erase cycles seen in flash (and other floating gate NVM). NOR flash and the erase phase of NAND flash are Fowler-Nordheim tunneling (every flash drive is proof of quantum mechanics being valid) which is less damaging but still damaging. So NOR flash tends to be a little better with endurance. As you get HCI damage, you progressive shift Vt's until the logic margin of the memory cell can no longer be detected by the array sense amps which basically means you can't detect a written bit any longer to read it out. Hence the flash memory is dead at its end-of-life.

 

[McKendrigo]

Hi jsgruszynski,

Thanks for your very detailed reply! I'll chew over it later when I have more time (and after a cup of coffee).

Cheers,
Jonny

 

[McKendrigo]

I thought I'd add my own little summary of the answers to my questions I got to with the help of jsgruszynski.

"if the channel has been pinched off, how can carriers readily flow between the source and drain?"

Near the drain, the inversion channel is 'pinched off'. However, there exists a reverse biased p-n junction (in an n-channel MOSFET, where p is the body and n is the drain) at the gate/drain interface where the end of the inversion channel is. The depletion region at this p-n interface results in an E field which attracts electrons from the end of the inversion channel towards the drain.

"How can increasing the drain voltage cause the channel resistance to both decrease and increase?"

The resistance increases because increasing Vd causes the channel to be 'pinched off', and made thinner. However, further increasing Vd pushes the pinched off channel closer towards the source. Since this physically reduces the overall size of the pinched off channel, this reduces the overall resistance of the channel.

There's a really nice animated tutorial here which I found useful. It allows you to change Vds and Vgs and observe what it does to the flow of current, the depletion and inversion regions etc.

http://www-g.eng.cam.ac.uk/mmg/teaching/linearcircuits/mosfet.html