Passing SD and HD video through a HPF

[Chrispp]

Good morning I have been browsing this forum for quite sometime finding very valuable information, but now I have a question of my own.

The very basic principles of RC HPF's tell us that all else equal the frequency and the value of the capacitance are inversely related. This suggests that the largest acceptable capacitance value should be much less for the higher frequency HD video then that of SD. However, after conducting many tests using the pathological test (PLL test simply strings 20 bits in a row together of 1's then 0's instead of having a transition every bit, effectively reducing the frequency in both SD and HD by the same factor) we have found some different results. The lowest acceptable capacitance values that do not kill the signal were MUCH lower for SD (1 micro compared to 4.7) than they were for HD. This seems to contradict first principles of HPF's, so what else is could be going on?

Any insight is greatly appreciated.

Regards,
Chris

 

[berkeman]

You would need to describe what you are doing in more detail -- it sounds like you are placing a crude RC filter in line with the RF feed? There are many factors involved, including impedance mismatches, signal encoding, preamp configurations, error correction codes, etc.

Can you please define explicitly what your experiment involves, and what the two different encoding schemes are (web pointers would be helpful).

Welcome to the PF, BTW.

 

[Chrispp]

Hey there, thanks for the reply.

So the whole question came about when my boss came to me with a little project asking why this might be the case. I do not know the details of the experiment that they were doing but he just asked for possible reasons why this could be happening, in any situation. I work for a company that builds semiconductor devices specifically for SD and HD Video Timing and Transport, such as equalizers, reclockers, cable drivers and clock cleaners.

The only information he gave me was the SD speed of 270Mb/s and the HD of 1.485Gb/s. Under the PLL test this works out to frequencies of 74.25MHz for HD and 13.5MHz for SD. He also told me that the lowest acceptable capacitance values in the HPF without killing the signal were 1 micro farad for SD and 4.7 micro farads for HD. He then told me to find out why this situation contradicts first principles of HPF's.

Thanks for the help,
Chris

 

[berkeman]

How exactly are these capacitors being placed? How is the data modulated? What is the nature of the signals in the coax?

The capacitance values are maybe the coax cable capacitances? Or some series capacitances for DC blocking somewhere? You say "HPF", implying highpass filter, which would mean the capacitor is in series for DC blocking. But what are the source and load impedances? 50 Ohms real, most likely.

Could you maybe post a link to some web pages that show the devices and such? If you're not supposed to post links to your own company's products here, maybe just post a link to a similar competitor's product line.

 

[chroot]

A larger capacitor has a lower resonant frequency. In other words, a larger capacitor produces an RC filter with a lower cut-off frequency. Your boss says SD signals, which are lower-frequency, can tolerate a 1 uF series cap, while HD signals, which are higher-frequency, can tolerate a 4.7 uF series cap. ("Tolerate" meaning, presumably, keeping some desired opening of the eye diagram.) This is contrary to first principles, since a higher frequency signal would demand a smaller series capacitance -- the opposite of what you're saying.

There could be myriad reasons why this is so: perhaps the characteristic impedances of your transmission lines are different, perhaps the HD drivers are beefier and able to source more current, etc.

- Warren

 

[Chrispp]

Thanks for the help so far,

Here's a link to some of the parts that are in consideration: http://www.gennum.com/video/vtt.htm

The tolerance is infact dealing with a desired opening of the eye diagram. The characteristics of the transmission lines are identical and has already been checked by the boss. He does infact have a degree in Electrical Engineer, and is just curious to some possible explanations of reasons why this might be going on. I have just completed my 2nd year in Electrical Engineering so I know he doesn't expect the world from me.

Thanks again, you guys have been very helpful.

Chris

 

[chroot]

The tolerance is infact dealing with a desired opening of the eye diagram. The characteristics of the transmission lines are identical and has already been checked by the boss.

Then I must assume you're using two different chips to drive the two different signals, yes? Presumably the HD one has bigger drivers, to achieve the necessarily higher slew rates. This means its output resistance is lower. As the output resistance gets smaller, the cut-off of the resulting RC gets higher.

- Warren

 

[Chrispp]

I believe we are using different chips to drive the signals in this case, as I know we do on a couple of different boards. I will have to check into specifics on Monday. Thanks for the help everyone, and enjoy your weekend :)


Chris

 

[berkeman]

Hey chroot, do you understand what capacitor Chrispp is referring to?

 

[chroot]

Hey chroot, do you understand what capacitor Chrispp is referring to?

No, I'm not entirely sure that I know what he's talking about at all.

In fact, if he's just talking about an AC coupling cap, in series with his receiver, then what he's really creating is an RC low-pass filter, which would explain why things seem backwards for him.

I wouldn't mind seeing a schematic.

- Warren

 

[Chrispp]

I do not know exactly where the capacitor is because I have no exactly been told. ALL I was given from my boss was the diagram of a HPF, and the equation f = (2*pi*R*C)^-1. He then told me he was using PLL test for both SD and HD video and came up with results that anything lower then 1uF kills SD and anything under 4.7uF kills the HD video. He asked for a reasonable explanation of why this might be happening.

So far what seems to me to be the most reasonable answer is the output impedance of the different chips could certainly raise the R not keeping it constant in both cases which will lead to bad results of the capacitance.

Thanks for the help guys :) made much progress.

Chris

 

[Chrispp]

So tomorrow is d-day. Based on the information I was given (apparently not much) is this what I should relay to my boss? It seems to me that he would have probably have realized that different chip drivers will cause a different output resistance, resulting in weird capacitance values..., but maybe he just overlooked the fact.

Thanks for the help guys, best forum for physics related help!

Chris

 

[berkeman]

Chrispp,

I think that you can relay what we've all talked about in this thread, but please also understand that chroot and I really aren't understanding what the full situation is here, so the real answers may be something different.

If chroot or I were tasked with a project like this, then I think you can tell that we would be looking in detail at all aspects of the situation, including what your supervisor is really doing with whatever capacitors and wherever they are "putting" them. So many things go into the error rate and error thresholds for transmission line systems -- I think it's a bit over-simplified to say something like "hey, this isn't acting like a highpass filter like I expected".

I think that the most productive thing you could do would be to sketch the two SD / HD transmission systems, including all components, encoding schemes, and other relevant aspects, and then show where in each your supervisor is "putting" the capacitor, and summarize the different things that might be going on. If you could include an impedance analyzer trace of the Z of the capacitors in the way that they are being hooked up, that will help some. And if you could use the gain-phase side of your impedance analyzer to plot the complex transfer function through the transmission system with and without the capacitors, that will probably be the most telling evidence of what is going on.

If your supervisor is just hacking capacitors of unknown RF characteristics into places where you normally don't put components, then the actual explanation for what is going on could have nothing at all to do with a simple RC filter effect. I hope that is fairly clear to you now from all of this.

Best of luck. See you around the PF.

 

[Chrispp]

As a follow-up from before, I've had another discussion recently with the boss as he was away at a trade show for the past few days. All I think he did was confuse me a little bit more, so any help is still greatly appreciated.

He told me that we are talking about exactly the same driver for both the SD and HD and this sort of stuff should not be taken into consideration as they have idealized the situation. The question is simply due to the test patterns that are being used. He drew out both the equalizer test (19 bits high, 1 low and then vise-versa) and the pathological test (20 bits high then 20 low), and suggested looking into the DC offset associated with both.

The only other new information he gave me was how the bit was randomized, which may or may not be useful. Its first (I believe he said 20 bits) into a scrambler which uses the function G1(x) = x^9 + x^4 + x. This output then goes into a NRZ to NRZI converter which uses the function G2(x) = x + 1. this output then heads into the serializer which produces a single 1 bit output.

Hopefully some of this information is a little more useful to you guys then myself. Any input would help.

Thanks,
Chris