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ciakamel
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A micro-instruction sequencing and execution machine has a clock cycle
time of 10 ns and a base Cycle Per Instruction (CPI) of 5. The possibility
of interrupts and (or) exceptions may happen in the middle of an
instruction that must have copies of the values of the registers at the
beginning of the instruction. These registers are usually called shadow
registers. Assume that the average instruction has two register operands
that must be restored on an interrupt. The interrupt rate is 100 interrupts
per second, and the interrupt cost is 30 cycles plus the time to restore the
shadowed registers, each of which takes 10 cycles. Analyze the
followings:
i) What is the effective CPI after accounting for interrupts?
ii) What is the performance loss from interrupts?
iii) Is 10 cycles to restore shadowed registers realistic?Anyone can help me with this question?
time of 10 ns and a base Cycle Per Instruction (CPI) of 5. The possibility
of interrupts and (or) exceptions may happen in the middle of an
instruction that must have copies of the values of the registers at the
beginning of the instruction. These registers are usually called shadow
registers. Assume that the average instruction has two register operands
that must be restored on an interrupt. The interrupt rate is 100 interrupts
per second, and the interrupt cost is 30 cycles plus the time to restore the
shadowed registers, each of which takes 10 cycles. Analyze the
followings:
i) What is the effective CPI after accounting for interrupts?
ii) What is the performance loss from interrupts?
iii) Is 10 cycles to restore shadowed registers realistic?Anyone can help me with this question?