Pretty simple NAND gate question

In summary, there was a conversation about two expressions: x1\uparrow(x2\uparrowx2) and x2\uparrow(x1\uparrowx2). The question was whether these two were equivalent or not. It was mentioned that ↑ represents a NAND gate operator. After discussing and examining truth tables, it was determined that these two expressions are not the same. One person also asked for clarification on how NAND gates are used in these expressions.
  • #1
DrummingAtom
659
2

Homework Statement



I was looking through some examples in my Digital Logic book and I stumbled across one that gave an answer of x1[itex]\uparrow[/itex](x2[itex]\uparrow[/itex]x2). The answer I got was x2[itex]\uparrow[/itex](x1[itex]\uparrow[/itex]x2).

After making a truth table I'm finding that these are not equal solutions. Unless, I'm doing something wrong.

The Attempt at a Solution



See above. Any help is appreciated.
 
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  • #2
DrummingAtom said:
x1[itex]\uparrow[/itex](x2[itex]\uparrow[/itex]x2).
Can you write this in words so I can see where NAND comes into it?
 
  • #3
NascentOxygen said:
Can you write this in words so I can see where NAND comes into it?

The problem asked to turn x1[itex]\overline{x}[/itex]2 + x2[itex]\overline{x}[/itex]1 into a NAND only circuit. I used decomposition in the last steps to get my answer.
 
  • #4
DrummingAtom said:
The problem asked to turn x1[itex]\overline{x}[/itex]2 + x2[itex]\overline{x}[/itex]1 into a NAND only circuit. I used decomposition in the last steps to get my answer.
Can you show the truth table for x1[itex]\overline{x}[/itex]2 + x2[itex]\overline{x}[/itex]1? I'm not sure the book answer is correct assuming that ↑ means NAND.
 
  • #5
I got my question answered today in class. Those two solutions are equivalent. Thanks for the help though.
 
  • #6
I'm somewhat confused by this. You never explained what ↑ means.

Isn't x1[itex]\overline{x}[/itex]2 + x2[itex]\overline{x}[/itex]1 the same as XOR? Wiki article for XOR implemented with NAND gates:

http://en.wikipedia.org/wiki/NAND_logic#XOR
 
  • #7
According to my book, ↑, is a NAND gate operator.
 
  • #8
OK, so again I ask what is the truth table for

x1[itex]\overline{x}[/itex]2 + x2[itex]\overline{x}[/itex]1

and the truth table for

x1↑(x2↑x2)

or

x2↑(x1↑x2)
 
  • #9
DrummingAtom said:
According to my book, ↑, is a NAND gate operator.
But a poor choice, and bound to lead to confusion.
 
  • #10
rcgldr said:
OK, so again I ask what is the truth table for

x1[itex]\overline{x}[/itex]2 + x2[itex]\overline{x}[/itex]1
Yes, that is exclusive NOR.

and the truth table for

x1↑(x2↑x2)

or

x2↑(x1↑x2)

x2 NAND x2 is just NOT x2

x2↑(x1↑x2) evaluates to x2 NAND NOT x1

So expressions in post #1 are NOT identical.
 
Last edited:

FAQ: Pretty simple NAND gate question

1. What is a NAND gate?

A NAND gate is a type of logic gate in digital electronics that performs the logical operation of negation AND. It outputs a high signal only when both of its inputs are low.

2. How does a NAND gate work?

A NAND gate works by using transistors to compare the inputs and produce the appropriate output. When both inputs are low, the transistors are turned on and the output is high. Otherwise, the transistors are turned off and the output is low.

3. What are the applications of a NAND gate?

NAND gates are commonly used in digital circuits for their ability to perform logical operations and create more complex functions. They are also used in memory devices, data processing, and in microprocessors.

4. Can a NAND gate be used for other logical operations?

Yes, a NAND gate can be used to perform other logical operations by combining multiple NAND gates together. For example, connecting the output of a NAND gate to the input of another NAND gate creates a NOT gate, which performs the logical operation of negation.

5. Are there any disadvantages to using a NAND gate?

One disadvantage of NAND gates is that they can introduce a delay in the output signal due to the time it takes for the transistors to switch on and off. Additionally, NAND gates require more complex circuitry compared to simpler gates, making them more expensive to produce.

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