- #1
pags920
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I have the following example that I need to compile in using Verilogger Pro. The example is that of a 4-bit universal shift register. We are told to take the code from our textbook and create a test bench. I am not worried about test bench at this time, I am having problems compiling the code. The code given to us is in 2001,2005 syntax. Our compiler will only work in 1995 syntax. I have narrowed down the errors to one line, but knowing how the program works, it could be anywhere, I cannot find it. I have mailed my TA about this almost 2 days ago and have not gotten a response.
My question is where is the error in my code?
Below is my error log:
Any ideas as to where the error is?
My question is where is the error in my code?
Code:
module Shift_Register_4_str (A_par, I_par, s1, s0, MSB_in, LSB_in, CLK, Clear);
output [3:0] A_par;
input [3:0] I_par;
input s1, s0, MSB_in, LSB_in, CLK, Clear;
assign [1:0] select = {s1,s0};
stage ST0 (A_par[0], A_par[1], LSB_in, I_par[0], A_par[0], select, CLK, Clear);
stage ST1 (A_par[1], A_par[2], A_par[0], I_par[1], A_par[1], select, CLK, Clear);
stage ST2 (A_par[2], A_par[3], A_par[1], I_par[2], A_par[2], select, CLK, Clear);
stage ST3 (A_par[3], MSB_in, A_par[2], I_par[3], A_par[3], select, CLK, Clear);
endmodule
module stage (i0, i1, i2, i3, Q, select, CLK, Clr);
input i0, i1, i2, i3;
output Q;
input [1:0] select;
input CLK, Clr;
wire mux_out;
Mux_4_x_1 M0 (mux_out, i0, i1, i2, i3, select);
D_flip_flop M1 (Q, mux_out, CLK, Clr);
endmodule
module Mux_4_x_1 (mux_out, i0, i1, i2, i3, select);
output mux_out;
input i0, i1, i2, i3;
input [1:0] select;
reg mux_out;
always @ (select or i0 or i1 or i2 or i3)
case (select)
2'b00: mux_out = i0;
2'b01: mux_out = i1;
2'b10: mux_out = i2;
2'b11: mux_out = i3;
endcase
endmodule
module D_flip_flop (Q, D, CLK, Clr);
output Q;
input D, CLK, Clr;
reg Q;
always @ (posedge CLK or negedge Clr)
if(~Clr)Q<=1'b0; else Q<=D;
endmodule
Below is my error log:
Code:
C:\Users\Muta\Desktop\HDL3\3-1b.v: L5: error: parse error, unexpected '[', expecting error or IDENTIFIER or HIERARCHY_IDENTIFIER or '{'
C:\Users\Muta\Desktop\HDL3\3-1b.v: L5: error: 'select' not declared
Any ideas as to where the error is?