- #1
michael_mke
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I have to design a counter using T flip-flops to count in the sequence 000, 100, 111, 010, 011, 000,...(repeat).
I think I got the code for the T flip-flop but not really sure and need some help implementing the counter with this.
Any help would be great. Thanks
//T flip-flop
I think I got the code for the T flip-flop but not really sure and need some help implementing the counter with this.
Any help would be great. Thanks
//T flip-flop
Code:
library ieee;
use ieee.std_logic_1164.all;
entity tff_sync_reset is
port (
data :in std_logic; -- Data input
clk :in std_logic; -- Clock input
reset :in std_logic; -- Reset input
q :out std_logic -- Q output
);
end entity;
architecture rtl of tff_sync_reset is
signal t :std_logic;
begin
process (clk) begin
if (rising_edge(clk)) then
if (reset = '0') then
t <= '0';
else
t <= not t;
end if;
end if;
end process;
q <= t;
end architecture;