Time Delay Chart: Understanding Circuit Diagram and Output Hazards

In summary, the conversation is about understanding how to draw a time chart for a circuit with inputs A, B, and C that emit a hazard at output Y. The time chart is drawn by tracing the propagation delays through the logic to determine how long it takes for changes at the inputs to propagate to the output. The circuit diagram shows that A starts as a 1 pulse, B goes from 1 to 0 at t0, and B' goes through an inverter and becomes a 1 at t1. This results in AB' becoming a 1 at t2. The conversation also discusses finding the number of propagation delay times it takes for changes at the inputs to affect the stability of output Y.
  • #1
MissP.25_5
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Hello, can someone please tell me how to draw this time chart? I got this from a friend and I don't understand how he got it.
A, B, C emit hazard at output Y.

Here are the circuit diagram and the time delay my friend drew.
 

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  • #2
looks like A starts out as 1 pulse

B goes from 1 to o at t0

B' goes thru the inverter and becomes a 1 at t1 (it takes time for the NOT gate to output the new state)

consequently AB' becomes a 1 at t2 (it takes time for the AND gate to output the new state)

Does that make sense?
 
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  • #3
jedishrfu said:
looks like A starts out as 1 pulse

B goes from 1 to o at t0

B' goes thru the inverter and becomes a 1 at t1 (it takes time for the NOT gate to output the new state)

consequently AB' becomes a 1 at t2 (it takes time for the AND gate to output the new state)

Does that make sense?

what about Y and what about B after t0? Could you explain those too so I can see how it goes? Please...
 
  • #4
He/she is just tracing the propagation delays through the logic to figure out how long it takes for changes at the inputs to propagate to the output Y.

What is the actual problem statement? The circuit looks related to your other thread, BTW?
 
  • #5
berkeman said:
He/she is just tracing the propagation delays through the logic to figure out how long it takes for changes at the inputs to propagate to the output Y.

What is the actual problem statement? The circuit looks related to your other thread, BTW?

My problem is how to know how long it takes.
 
  • #6
MissP.25_5 said:
My problem is how to know how long it takes.

How long what takes? Do you need to find how many prop delay times (tpd) it takes from one of the inputs changing until Y is stable? Which input(s)?
 

Related to Time Delay Chart: Understanding Circuit Diagram and Output Hazards

1. What is a time delay chart and how is it used in circuit design?

A time delay chart is a graphical representation of the time delay between inputs and outputs in a circuit. It is used to understand the timing behavior of a circuit and to identify potential hazards, such as output glitches or race conditions.

2. How is a time delay chart created?

To create a time delay chart, the propagation delays of each component in the circuit must be determined. These delays are then plotted on a graph, with the input signals on the horizontal axis and the output signals on the vertical axis. This allows for a visual representation of the timing behavior of the circuit.

3. What are output hazards and how are they identified on a time delay chart?

Output hazards are unwanted transitions or glitches in the output of a circuit. They can be caused by race conditions, where the output of a circuit changes unpredictably due to varying input delays. On a time delay chart, output hazards can be identified as non-monotonic slopes or overlapping input and output signals.

4. How can time delay charts help in avoiding output hazards?

By analyzing a time delay chart, potential hazards can be identified and addressed in the circuit design phase. This can include adjusting component placement or adding delay elements to ensure that the circuit functions as intended and avoids output hazards.

5. Are there any limitations to using time delay charts?

Time delay charts are a useful tool in understanding circuit timing behavior, but they do have limitations. They assume ideal conditions and do not account for factors such as temperature, voltage variations, and component tolerances. Additionally, they may not accurately reflect the behavior of complex circuits with multiple inputs and outputs.

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