- #1
likephysics
- 636
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I am trying to understand when clamping diode (at TTL gate input) works and when it does not.
The voltage is -2v at cathode and 0v at anode. Fwd bias condition, but the diode does not condut, until the current is reduced.
Why so?
Initially I thought it was because of the fast rise/fall times (1ns), but now in simulation as I reduce the current, it starts to clamp.
Ckt diagram attached. Please ignore the component values.
Current is reduced using Resistor R3.
C1 and R4, produce undershoots. Just a high pass filter with 5Vpk-pk square wave input.
The voltage is -2v at cathode and 0v at anode. Fwd bias condition, but the diode does not condut, until the current is reduced.
Why so?
Initially I thought it was because of the fast rise/fall times (1ns), but now in simulation as I reduce the current, it starts to clamp.
Ckt diagram attached. Please ignore the component values.
Current is reduced using Resistor R3.
C1 and R4, produce undershoots. Just a high pass filter with 5Vpk-pk square wave input.