- #1
demLara
I have a understanding problem with the JFET Transistor. I need this for the exam.
Gate-Source Voltage = 0V.
How are the PN Junction biased between Drain and Gate and Gate and Drain.
For the following cases.
Vds = 0V this sould be the thermal equilibrium
Vds < Vdsat (both reverse ?)
Vds > Vdsat (both reverse ?)
The exercise is i have to draw the bandstrucutre at source contact and in the pinched off region at the drain contact.
Gate-Source Voltage = 0V.
How are the PN Junction biased between Drain and Gate and Gate and Drain.
For the following cases.
Vds = 0V this sould be the thermal equilibrium
Vds < Vdsat (both reverse ?)
Vds > Vdsat (both reverse ?)
The exercise is i have to draw the bandstrucutre at source contact and in the pinched off region at the drain contact.
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