- #36
samski
- 60
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no it actually takes the difference in phase between the input and the output sinusoids. that's why there is a "phase detector". think about it, if what you said is right, then when the input frequency and the LO frequency are the same, there would be no voltage, so what is driving the VCO??yungman said:But as I said, the input to the PLL has to be frequency. that's how PLL work, you have a LO, you input a certain frequency [itex]\omega[/itex], the PLL will take the difference between the input frequency and the LO frequency and generate a voltage.
that is where [itex]V_1 =K(\theta_0-\theta_{ref})[/itex]. Before it lock, the difference in phase between the two will create a voltage V1 that move the LO towards the in coming frequency. Then it become DC when the frequencies equal and lock. Under modulation, V1 will show the modulation. PLL is a down converter like IF stage of a AM or FM radio.
imagine you put an oscilloscope on the input to the PLL. you see a sinusoid yea? that's the x in my equation, x=sine(f(t)) is a sinusoid that is progressed according to a function of time.