Verilog - generate random delay time in testbench

In summary, the conversation discusses the process of generating a random delay time and value in a testbench. The individual has created a for-loop to generate a range of random time and then uses a value b in the generated delay time. However, there is an error with the syntax, and the individual is asking for clarification on how to properly use the # symbol for delays. They are also considering using two for-loops to change the maximum and minimum values.
  • #1
hoheiho
47
0

Homework Statement


Hi, I would like to generate a random delay time and value in testbench. This is what I did:

Code:
for(i=0;i<300;i=i+30)
  begin
  j = i + {$random} % (300 - i) // MIN + {$random} % (MAX - MIN )
  #j b = {$random} %3;
  #3ns b = 3'b000;
  end

I want to generate random value in random time. int i give me the range of random time. j is the actual random delay timing and b is the random value.
What I want to do here is generate a range -> generate delay time-> use value b in the the generated delay time -> recover value b after 3ns.

But it comes out error with:
**near "#": syntax error, unexpected '#', expecting ';'

Is that mean I can only use a actual value for the delay? Like #30, #20...but not a unknown value #j ? I have google it but cannot find any useful information about my problem..

Thank you very much for the help
Ivan
 
Last edited:
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  • #2
Hi hoheiho!

Looks like you have it right.
Suppose you create a for-loop up to j and wait #1 each time?
 
  • #3
Thank for your reply
Sorry for my poor english, I didnt get what you mean by wait #1ns? I would like to create a for loop and get the random delay timing between 0 ns to 300ns. It will generate a random delay time each 30ns. (i=0;i<300;i=i+30).
For example
0 ns to 30ns:
j = 20ns -> inject value b at time 20ns -> recovery back to b = 3'b000 at time 23ns -> start next for loop cycle ->
30ns to 60ns:
...
..
.
 
  • #4
Now that I look again, didn't you forget a ';' on the line before your error?


Btw, instead of waiting with #j, you can also wait with:
Code:
for(k=0;k<j;k=k+1)
  begin
  #1ns ;
  end
 
  • #5
Sorry for the typing error again :(.

When I do the simulation, the code doesn't work what I prefer. I think I need to use two for loop together to change the MAX and MIN value. I am trying to fix it now.

Thanks :)
 

FAQ: Verilog - generate random delay time in testbench

1. How can I generate a random delay time in my Verilog testbench?

To generate a random delay time in Verilog, you can use the $random system function. This function returns a random integer value between 0 and the specified maximum value. You can use this value to create a delay time in your testbench.

2. Can I specify a range for the random delay time?

Yes, you can specify a range for the random delay time by using the $urandom system function. This function returns a random unsigned integer value within the specified range. You can then use this value to create a delay time in your testbench.

3. How can I ensure that the random delay time is within a specific range?

You can use the $urandom_range system function to specify a specific range for your random delay time. This function returns a random integer value between the specified minimum and maximum values. You can then use this value to create a delay time in your testbench.

4. Can I use a seed value to generate a reproducible random delay time?

Yes, you can use the $srandom system function to set a seed value for your random number generation. This will ensure that the same sequence of random numbers is generated every time your testbench is run, making your results reproducible.

5. Are there any other methods for generating a random delay time in Verilog?

Yes, there are other methods for generating a random delay time in Verilog, such as using the $dist_uniform system function or using a random number generator module. However, the $random, $urandom, and $urandom_range functions are the most commonly used and recommended methods.

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