- #1
Steve198402
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I'm super confused on why I keep getting an error on this code. I feel like I've tried everything but now I've run into mental block lol. My error message is:
Error (10380): VHDL error at lab2.vhd(6): std_logic type is used but not declared as an array type
Here is the code I came up with.
Mind you, I started on VHDL last week so I know there is a lot I still need to grasp for this language.
Error (10380): VHDL error at lab2.vhd(6): std_logic type is used but not declared as an array type
Here is the code I came up with.
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY lab2 IS
PORT(
A: IN BIT_VECTOR (3 downto 0);
Y: OUT STD_LOGIC (9 downto 0));
END lab2;
ARCHITECTURE CIRCUIT OF lab2 IS
BEGIN
WITH A SELECT
Y<= "1111110" WHEN "0000",
"0110000" WHEN "0001",
"1101101" WHEN "0010",
"1111001" WHEN "0011",
"0110011" WHEN "0100",
"1011011" WHEN "0101",
"1011111" WHEN "0110",
"1110000" WHEN "0111",
"1111111" WHEN "1000",
"1110011" WHEN "1001";
END CIRCUIT;
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