What are the Vgd and Vgs of the Load NMOS in This NMOS Loaded NMOS Inverter?

  • Thread starter InuyashaITB
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In summary, the given values for Vdd, Vgg, Kn', (W/L)o, (W/L)L, and Vt are used to determine the Vgd and Vgs of the load NMOS. The load NMOS is always in linear mode, with the Id equation being Id = Kn[(Vgsl – Vt)Vdsl – 0.5*Vdsl^2]. Kn = Kn'*W/L, with (W/L)o and (W/L)L being the width over the length of the channel for the upper and lower transistors, respectively. Vi can vary from 0 to Vdd, and the VTC curve and all critical points (Vm, Voh, Vol, Vih,
  • #1
InuyashaITB
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Homework Statement


NMOS%20inverter_zpshjemzera.png

Given
Vdd = 5v, Vgg = 10v, Kn' = 20uA/V^2 (For both transistors), (W/L)o = 10um/5um, (W/L)L = 5um/20um, Vt = 1.1V (for both)

My question is what would be the Vgd, and Vgs of the load NMOS?

Homework Equations


upload_2015-9-19_12-50-11.png

The Attempt at a Solution


So far, what i have is:
The NMOS Load is always in linear mode. Id = Kn[(Vgsl – Vt)Vdsl – 0.5*Vdsl^2]

Vi = Vgso

Vo = Vdso
 
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  • #2
(W/L)o = 10um/5um, (W/L)L = 5um/20um
What are these?

Kn' = 20uA/V^2
Why Kn'? why the prime?

 
  • #3
The W/L is the width over the length of the channel of the transistors. Basically Kn = Kn'*W/L
 
  • #4
rude man said:
(W/L)o = 10um/5um, (W/L)L = 5um/20um
which is which? does "o" stand for the upper and "L" for the lower transistor?
also need to know Vi.
 
  • #5
The O is the lower transistor, the L is the upper transistor (L for Load)
 
  • #6
InuyashaITB said:
The O is the lower transistor, the L is the upper transistor (L for Load)
Vi?
 
  • #7
Vi would be variable, from 0 to Vdd
 
  • #8
The original question to this problem is to re-create its VTC curve and find all of the critical points of the VTC (Vm, Voh, Vol, Vih, Vil, NMh, NML, and power dissipation
 
  • #9
InuyashaITB said:
Vi would be variable, from 0 to Vdd
It can vary all the way from 0V to 5V? That would make the problem a tall order. Do you have pspice? :smile:

Or maybe Vi is either 0V or 5V? That we could live with ...
 
  • #10
rude man said:
It can vary all the way from 0V to 5V? That would make the problem a tall order. Do you have pspice? :smile:

Or maybe Vi is either 0V or 5V? That we could live with ...

Yes, if we look at the extremes it would help
 
  • #11
InuyashaITB said:
Yes, if we look at the extremes it would help
OK. Because if you allow the entire range from 0 to 5V one or both devices will transition from one mode to another, making for a headache unless you do it with some kind of software. You could use spice or write your own high-level-language program.
Also, your statement that the load FET is always in the linear mode is incorrect sice there is effectively nothing connected to its source if Vi = 0.
Stay tuned.
 
  • #12
I simulated the circuit exactly as described
https://goo.gl/photos/bHLqKvAJKTMKLym86

It seems Voh=5v
Vol=1v
Vm = 2.5v

This is all according to simulation, would this be close to what the theoretical should be
 
  • #13
I will try to do a computation for Vi = 5V and 1V, maybe 2.5V also. Later.
EDIT: instead I will give you suggestions on how to proceed:
1. You have the L fet always in the linear mode, as you say.
2. assume the o fet is also in the linear mode. Equate the two fets' equations since the current is the same. Solve for all voltages. If the voltages meet the requirements for the linear mode for the o fet, you're done.
3. if not, then assume the o fet is in the saturated mode and repeat solving for all the voltages the same way.
For Vi = +2.5V and +5V the o fet has to be in either the linear or saturated mode.
For Vi = +1V it should be obvious what the mode of the o fet is.
Your simulation looks about right.
Remember you have Vd1 = Vs2 etc. The only unknown is Vd1 = Vs2.
P.S. an excel spreadsheet might be a good way to do this.
 
Last edited:
  • #14
rude man said:
I will try to do a computation for Vi = 5V and 1V, maybe 2.5V also. Later.
EDIT: instead I will give you suggestions on how to proceed:
1. You have the L fet always in the linear mode, as you say.
2. assume the o fet is also in the linear mode. Equate the two fets' equations since the current is the same. Solve for all voltages. If the voltages meet the requirements for the linear mode for the o fet, you're done.
3. if not, then assume the o fet is in the saturated mode and repeat solving for all the voltages the same way.
For Vi = +2.5V and +5V the o fet has to be in either the linear or saturated mode.
For Vi = +1V it should be obvious what the mode of the o fet is.
Your simulation looks about right.
Remember you have Vd1 = Vs2 etc. The only unknown is Vd1 = Vs2.
P.S. an excel spreadsheet might be a good way to do this.
So what would be the Vgs of the O transistor seeing as how there is a Vgg tied to the O transistor
 
  • #15
rude man said:
I will ty to do a computation for Vi = 5V and 1V, maybe 2.5V also. Later.
InuyashaITB said:
So what would be the Vgs of the O transistor seeing as how there is a Vgg tied to the O transistor
 
  • #16
InuyashaITB said:
So what would be the Vgs of the O transistor seeing as how there is a Vgg tied to the O transistor
You mean QL, not "the O transistor", right? To avoid further confusion, I am using the subscript "1" for Qo and "2" for QL henceforth:
You have every voltage except Vd1 which is also Vs2:
Vg1 = Vi (i.e. 1V, 2.5V and/or 5v)
Vg2 = +10V
Vd2 = +5V
Vs1 = 0
So, solve for Vd1 which is also Vs2.
 

FAQ: What are the Vgd and Vgs of the Load NMOS in This NMOS Loaded NMOS Inverter?

Q: What is a NMOS Loaded NMOS inverter?

A NMOS Loaded NMOS inverter is a type of electronic circuit that utilizes NMOS (N-channel metal oxide semiconductor) transistors to invert the input signal. It is used in digital logic circuits and is an essential component in the design of integrated circuits.

Q: How does a NMOS Loaded NMOS inverter work?

In a NMOS Loaded NMOS inverter, the input signal is connected to the gate of the first NMOS transistor, while the output is connected to the drain of the second NMOS transistor. The source of both transistors is connected to ground. When the input signal is low, the first NMOS transistor is turned off, and the second NMOS transistor is turned on, allowing current to flow from the power supply to the output, resulting in a high output signal. When the input signal is high, the first NMOS transistor is turned on, and the second NMOS transistor is turned off, cutting off the current flow and resulting in a low output signal.

Q: What are the advantages of using a NMOS Loaded NMOS inverter?

Some advantages of a NMOS Loaded NMOS inverter include its simplicity, low power consumption, and fast switching speed. It also has a high noise margin, making it less susceptible to external interference. Additionally, it can be easily integrated into larger circuits due to its small size.

Q: What are the limitations of a NMOS Loaded NMOS inverter?

One limitation of a NMOS Loaded NMOS inverter is that it can only be used with digital signals, not analog signals. It also has a limited output voltage range, which can cause distortion in the output signal. Additionally, it is vulnerable to latch-up, which can occur when the input voltage exceeds the power supply voltage, causing the transistors to remain in the on state and potentially damaging the circuit.

Q: How is a NMOS Loaded NMOS inverter different from a CMOS inverter?

While both a NMOS Loaded NMOS inverter and a CMOS inverter are types of digital logic circuits, they differ in the type of transistors used. A NMOS Loaded NMOS inverter uses only NMOS transistors, while a CMOS inverter uses both NMOS and PMOS (P-channel metal oxide semiconductor) transistors. CMOS inverters also have a lower power consumption and a wider output voltage range compared to NMOS Loaded NMOS inverters.

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