- #1
littlebilly91
- 22
- 0
I am doing a discrete event simulation of logic gates and I have come upon a problem. I have set up a system similar to a ring oscillator. I understand that this system should not oscillate, but after thinking about it, I'm not sure why not. The system has one input, 1 fed into a NAND gate. The NAND feeds into a NOT and the not feeds back into the original NAND. This is similar to an even number of NOTs so it shouldn't oscillate, but any time I analyze it step by step it seems like it still would. Here is my thinking:
At time 0:
Both gates output a 0.
The NAND sees a 1 from the output and a 0 from the NOT gate
The NOT sees a 0 from the NAND
Both the NAND and the NOT will switch to 1 after a propagation delay.
After one delay:
Both gates output a 1.
The NAND sees a 1 from the output and a 1 from the NOT gate
The NOT sees a 1 from the NAND
Both the NAND and the NOT will switch to 0 after another propagation delay.
repeat forever...
I assumed the delays are the same, is that where the mistake lies? The digital logic class I am in is solely focused on the logic so I don't really know any different.
At time 0:
Both gates output a 0.
The NAND sees a 1 from the output and a 0 from the NOT gate
The NOT sees a 0 from the NAND
Both the NAND and the NOT will switch to 1 after a propagation delay.
After one delay:
Both gates output a 1.
The NAND sees a 1 from the output and a 1 from the NOT gate
The NOT sees a 1 from the NAND
Both the NAND and the NOT will switch to 0 after another propagation delay.
repeat forever...
I assumed the delays are the same, is that where the mistake lies? The digital logic class I am in is solely focused on the logic so I don't really know any different.