Worst-case power consumed by a circuit with MOSFETs

In summary, the worst-case power consumed by a circuit with MOSFETs occurs during the maximum load conditions when the MOSFETs are fully on (saturation) or fully off (cutoff). The power consumption can be calculated using the formula P = I²R for the on-state and includes switching losses during transitions. Factors influencing power consumption include the load resistance, supply voltage, and the frequency of operation. Proper design and optimization of these parameters are essential to minimize power loss and improve efficiency in MOSFET-based circuits.
  • #1
zenterix
708
84
Homework Statement
Consider the circuit depicted below. Use the Switch-Resistor model for the MOSFETs.

Assume ##R_6=R_7=10\mathrm{k\Omega}##, the threshold voltage for the MOSFETs is ##\mathrm{2V}##, and the resistance of the MOSFET in its ON state is ##\mathrm{1k\Omega}##.

Compute the worst-case power consumed by this circuit.
Relevant Equations
##P=iV##
Here is the circuit.
1706844518821.png


Note that no current flows between the left and right sides of the circuit: their only relationship happens through the MOSFET that is parallel to B.

There are eight cases to consider: all the combinations of ON/OFF for the three MOSFETs.

Here is a summary of the eight cases according to my calculations

1706844476952.png


It seems that the highest power consumption occurs when all MOSFETs are on.

Here is more in depth explanation of how the table above was created.

It seems that whether MOSFET C is on or off, the voltage at the node right above it (beneath resistor R7) is higher than ##V_T=\mathrm{2V}##.

Thus, the MOSFET in parallel with B is always on.

Let's consider just the left side of the circuit for now.

If ##A## is off, then no current flows so ##i=0##.

Suppose A is on.

Then we have two cases:
B on, B off.

If B is on, then the left side of the circuit becomes

1706843242280.png


##i=\frac{5}{11.5\cdot 10^3}\text{A}## and ##v_{OUT}=\frac{10}{11.5}\cdot 5\text{V}##.

Power consumed by this subcircuit is ##i\cdot V_S=5\cdot\frac{5}{11.5\cdot 10^3}\mathrm{\frac{J}{S}}##.

If, on the other hand, B is off then the only difference is that the resistance that is ##1/2\mathrm{k\Omega}## above becomes ##1\mathrm{k\Omega}##.

Thus, ##i=\frac{5}{12\cdot 10^3}\mathrm{A}## and ##v_{OUT}=\frac{10}{12}\cdot 5=\frac{25}{6}\text{V}##.

Now consider the right side of the circuit.

Suppose ##C## is on. Then the current on the right side (call it ##i_2##) will be ##i_2=\frac{5\text{V}}{11\cdot 10^3}\text{A}##.

If ##C## is off, then no current flows on the right side.

Finally, to obtain power consumption I simply computed ##P=i\cdot V_S+i_2\cdot V_S## for all eight cases.

Is this the correct calculation?
 
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  • #2
The ON resistance of the MOSFET is kilo-ohms??? Seems odd.
 
  • #3
Here is the problem statement in full. From this problem set of MIT OCW's 6.002

1708291477245.png


The cited exercise from Agarwal's books is

1708291533867.png


and here is Figure 6.59(c)

1708291600986.png

Thus, the ON resistance is indeed 1 kilo-ohm.
 

FAQ: Worst-case power consumed by a circuit with MOSFETs

What factors contribute to the worst-case power consumption in a MOSFET circuit?

The worst-case power consumption in a MOSFET circuit is influenced by several factors, including the supply voltage, the switching frequency, the load capacitance, the on-resistance of the MOSFETs, and the leakage currents. High supply voltage and switching frequency increase dynamic power consumption, while high on-resistance and leakage currents contribute to static power consumption.

How does switching frequency affect the worst-case power consumption of a MOSFET circuit?

Switching frequency significantly impacts the dynamic power consumption of a MOSFET circuit. Higher switching frequencies lead to more frequent charging and discharging of load capacitances, which increases the dynamic power dissipation. The power consumed is proportional to the frequency, load capacitance, and the square of the supply voltage.

What is the role of leakage current in the worst-case power consumption of MOSFET circuits?

Leakage current, which flows even when the MOSFET is in the off state, contributes to static power consumption. In modern MOSFET circuits, particularly those with smaller geometries, leakage currents can be substantial and significantly impact the worst-case power consumption. Minimizing leakage is crucial for reducing static power dissipation.

How can the worst-case power consumption be estimated for a given MOSFET circuit?

To estimate the worst-case power consumption, one needs to consider both dynamic and static power components. Dynamic power can be calculated using the formula P_dynamic = α * C_load * V_dd^2 * f, where α is the activity factor, C_load is the load capacitance, V_dd is the supply voltage, and f is the switching frequency. Static power is primarily due to leakage currents and can be estimated using P_static = I_leakage * V_dd. Summing these components gives the total worst-case power consumption.

What design strategies can be employed to minimize worst-case power consumption in MOSFET circuits?

Several design strategies can help minimize worst-case power consumption in MOSFET circuits. These include using low-leakage MOSFETs, optimizing the supply voltage, reducing the switching frequency, minimizing load capacitance, and implementing power gating techniques to cut off power to inactive circuit sections. Additionally, using proper sizing and layout techniques to reduce parasitic capacitances can also help in lowering power consumption.

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