Writing About an Operation: 3-bus CPU

[naspek]

Hey guys... here is the thing.. i kinda blur to talk about the operation..
i need help from u guys to give me ideas to write about the operation..
i attempted the question already.. but, i think it wasn't enough explanations.

[PLAIN]http://img401.imageshack.us/img401/8831/74967107.jpg

 

[berkeman]

Hey guys... here is the thing.. i kinda blur to talk about the operation..
i need help from u guys to give me ideas to write about the operation..
i attempted the question already.. but, i think it wasn't enough explanations.

[PLAIN]http://img401.imageshack.us/img401/8831/74967107.jpg[/QUOTE]

Looks like a good start. Discuss what kinds of operations would benifit from having two input busses for the ALU.

 

[naspek]

Got it! Thanks! =)

 

[naspek]

can someone give me ideas to start answering part (ii) question?

 

[berkeman]

can someone give me ideas to start answering part (ii) question?

Part ii did not translate very well. Can you explain better what they want?

 

[naspek]

ok.. here what i understand from the question..
"Draw a CPU architecture using one logic gate, which control instruction by Registers (left) and ALU (right)"

is it clear?

 

[berkeman]

ok.. here what i understand from the question..
"Draw a CPU architecture using one logic gate, which control instruction by Registers (left) and ALU (right)"

is it clear?

That helps with the left/right part. But how in the world can you draw an "architecture" with just one gate? Do they meay just one kind of gate, but lots of them? If so, which gate would you choose, and why?

 

[naspek]

That helps with the left/right part. But how in the world can you draw an "architecture" with just one gate? Do they meay just one kind of gate, but lots of them? If so, which gate would you choose, and why?

ok.. i really got no idea.. been searching on the net, but still no idea..
do u have any link/resource i can go to? to get better understanding..
coz, honestly, my lecturer didn't mention any of these during classes..

 

[berkeman]

ok.. i really got no idea.. been searching on the net, but still no idea..
do u have any link/resource i can go to? to get better understanding..
coz, honestly, my lecturer didn't mention any of these during classes..

Well, you didn't answer my question about the "one gate" thing, but whatever.

This wikipedia page is an introduction to logic gates, and it has the answer to my question about what gate to choose if you can only use one type of gate:

http://en.wikipedia.org/wiki/Logic_gates

Your lecturer must have at least described basic computer architecture, if he/she gave you this assignment, correct?

 

[naspek]

Well, you didn't answer my question about the "one gate" thing, but whatever.

This wikipedia page is an introduction to logic gates, and it has the answer to my question about what gate to choose if you can only use one type of gate:

http://en.wikipedia.org/wiki/Logic_gates

Your lecturer must have at least described basic computer architecture, if he/she gave you this assignment, correct?

ok.. regarding your question.. my lecturer said it was typo error..
it should be BY USING ANY ONE LOGIC GATE... so, i need to use only one logic gate..

Both "left" and "right" are referring to the "instruction".

and.. yes.. he did talk about computer architecture.. but.. he didn't mention any logic gate..
nevermind..

so.. my question now.. after i choose my logic gate, how am i going to draw the architecture..?

 

[berkeman]

ok.. regarding your question.. my lecturer said it was typo error..
it should be BY USING ANY ONE LOGIC GATE... so, i need to use only one logic gate..

Both "left" and "right" are referring to the "instruction".

and.. yes.. he did talk about computer architecture.. but.. he didn't mention any logic gate..
nevermind..

so.. my question now.. after i choose my logic gate, how am i going to draw the architecture..?

Well, to draw an architecture, you generally start at the block diagram level. Then you can add more details with function blocks underneath the block diagram level. And then finally you would draw the logic gates (or the Verilog code) details underneath the function blocks within the block diagram. Even a simple architecture will contain thousands of gates, so I'm thinking that the problem statement still isn't translating well, or contains more typos.

Sorry to not be of more help, but the problem statement makes no sense as written, IMO.

 

[naspek]

I know right.. it doesn't make any sense..
i've been argue it with my lecturer for about half an hour..
still he said the question is right and there's answer for the question given.. what to do..

nevermind.. it's very kind of u to help me..

Thanks berkeman.. ^_^

 

[berkeman]

What is the original language of the question? I still wonder if the translation is hindering our exchange. Not that I would be able to read the original question in a different language...

The only suggestion I can offer is to try to look for a solution that does not require many gates. They can't be asking you to draw a full computer architecture with thousands or millions of gates. They must be asking for some intermediate information, showing a dozen gates or so, for multiplexing the registers onto the busses, and sending the result back to the registers. But beyond that, I have no idea what they are asking for. Sorry.

 

[berkeman]

One other thought. You could provide a pointer to this thread to your instructor, to show how the problem did not translate very well into a traditional computer architecture/logic question. Perhaps that would help him/her to phrase their questions better in the future.