Need a voltage divider for a capacitor source voltage

[imsmooth]

Made a solid ground. Connected the divider. No difference and still wrong measurements. Then, as a guess I disconnected the p5205 differential probe and held it in the air. I was seeing the strange waveform.

Apparently, my probe has issues and I was never making a proper measurement. I switched probes and now I can see the proper phase shift. I'm still not seeing a 1:100 division, but it is better. I'm going to buy another probe.

I know the p5205 is no longer serviceable. Any suggestions for a good replacement. p5205a?

 

[Baluncore]

Made a solid ground. Connected the divider.

I tried mind reading, but I am not doing well today, you are going to have to help me.
What or where did you ground something?
What sort of divider did you use?
How did you connect the divider?
Maybe it is time for you to use LTspice to draft an up-to-date circuit diagram. It does not have to run correctly.

If you change an LTspice.asc file to LTspice.asc.txt , you can attach it to a post, then others can run and edit it. That is the most compact way to communicate circuit diagrams clearly.

Do not post screenshots.
Alternatively, use the "Tools" menu, "copy bitmap to clipboard".
Save the image as a .png or .jpg

 

[TonyStewart]

I know the p5205 is no longer serviceable. Any suggestions for a good replacement. p5205a?

The Diff. Probe P2505 only has a CMRR of > 300 @ 100 kHz. or <-30dB error. So a good ground is essential on the signal with a short ground connection. Verify again with both inputs and gnd to gnd for a flat trace.

Probing the HV output will radiate EMI measurement problems beyond the scope of this thread. only use the C divider output.
You can improve it further with 100 pF\10 nF ( Z(f)= 212 Ohms @ 75kHz to probe.

 

[imsmooth]

I tried mind reading, but I am not doing well today, you are going to have to help me.
What or where did you ground something?
What sort of divider did you use?
How did you connect the divider?
Maybe it is time for you to use LTspice to draft an up-to-date circuit diagram. It does not have to run correctly.

If you change an LTspice.asc file to LTspice.asc.txt , you can attach it to a post, then others can run and edit it. That is the most compact way to communicate circuit diagrams clearly.

Do not post screenshots.
Alternatively, use the "Tools" menu, "copy bitmap to clipboard".
Save the image as a .png or .jpg

Still learning how to use LTspice. Below is the LTSpice tank model. All these years I should have started using it. The tank is modeled pretty close to how mine works.

 

[imsmooth]

Verify again with both inputs and gnd to gnd for a flat trace.

Probing the HV output will radiate EMI measurement problems beyond the scope of this thread. only use the C divider output.
You can improve it further with 100 pF\10 nF ( Z(f)= 212 Ohms @ 75kHz to probe.

You're saying to short the probe ends together or to test them on the grounding lead?

When you say only use the C divider output are you referring to a capacitative divider or something else?

 

[TonyStewart]

You're saying to short the probe ends together or to test them on the grounding lead?

YES by connecting both inputs to either signal and ground, you are measuring the CMRR and crosstalk. So expect it must be a flat line.

When you say only use the C divider output are you referring to a capacitative divider or something else?

YES and it's called "capacitive" and not capacitative.

 

[imsmooth]

YES by connecting both inputs to either signal and ground, you are measuring the CMRR and crosstalk. So expect it must be a flat line.

When you say only use the C divider output are you referring to a capacitative divider or something else?

YES and it's called "capacitive" and not capacitative.

When I connect both leads together they are picking up significant EMI when I power up my device. I suspect something is not working with the probes. Any suggestions to troubleshoot them or the power supply (1103)?

 

[TonyStewart]

When I connect both leads together they are picking up significant EMI when I power up my device. I suspect something is not working with the probes. Any suggestions to troubleshoot them or the power supply (1103)?

You will have to show a picture of everything with all power sources with schematic showing nodes, and sources of AC. SMPS (DC) are notorious for leakage of CM noise when isolated. Then we can analyze and fix.

 

[imsmooth]

I can get there tomorrow and see what I can do. However, I just connected both probe ends to a ground wire and I do not get a flat line. When I power on a high frequency device nearby I see a high voltage signal on the scope. Not sure what else there is to show. Seems like something is broken.

 

[imsmooth]

After switching to a standard probe I was able to get the correct values and waveforms using a resistor divider as well as a capacitor divider. Both worked as predicted.

The problem was with the differential probe and the noise overwhelming the signal. I am done with this thread and will try to address the probe issues in my other thread.

 

[Baluncore]

Edited LTspice schematic and plot files attached.
Includes notes on simulation, and a 101:1 voltage divider.

 

[imsmooth]

Edited LTspice schematic and plot files attached.
Includes notes on simulation, and a 101:1 voltage divider.

thanks for the edits. I have some questions now as I'm trying to learn how to use LTSpice.
1. How did you separate the "pulse" command from the voltage source. I tried to move it by I just moved everything. I hovered over to no avail.

2. Where did you get the "ferrite core" for the transformer and put it in-between L2 and L3? Did you just draw vertical wires? Doesn't the K1 command link the two inductors together so why do I need to draw the core or is it just aesthetics?

3. How does the wire connection at the bottom between L2 and L3 change the behavior from my original schematic? I can see when I remove it the voltages change.
4. How is setting the V(a) condition changing the analysis much other than setting the initial voltage to 240? Is it necessary? In reality, aren't both voltages really zero in the beginning?
4b. How did you enter the label "a"
5. what is the value of 7m15 and 20m? Is 20m 20mH? What is 7m15 then? 7.15mH?
6. How is the behavior of the voltage divider with the parallel capacitors different/better than just one or the other.
7. How do I open the .plt file for viewing?

I know it's a lot of questions and I appreciate your help.

 

[Baluncore]

1. How did you separate the "pulse" command from the voltage source. I tried to move it by I just moved everything. I hovered over to now avail.
Select the 'move' or 'drag' hand to select the text you want to move away from the source. I try to keep the head-end of the text under its voltage source, so I can find it and do not get confused with multiple sources.

2. Where did you get the "ferrite core" for the transformer and put it in-between L2 and L3
I drew it using isolated track segments. Iron cores get a couple of parallel tracks, or sometimes the rotated coupling coefficient text.

3. How does the wire connection between L2 and L3 change the behavior from my original schematic
It provides the required ground reference to the secondary side of the transformer. It does it in a way that shows it must be part of the connections. Don't forget that grounds between modules are all hidden connections.

4. .IC Va...which voltage is Va
.IC V(a) is the initial voltage on node a of the circuit = capacitor voltage relative to ground. I left the inductor current and flux at zero, but guessed the V(a)=240 to avoid the 0.5 second of simulation needed to get the voltage symmetrical about zero. I left the first couple of cycles showing during the transient analysis.

5. what is the value of 7m15 and 20m? Is 20m 20mH? What is 7m15 then?
The SI prefix takes the place of the decimal point. It is easier to read fast, or on a poorly printed circuit diagram.
20m = 20.0m = 20.0 mH = 0.02 H = 2e-2 H.
7m15 = 7.15m = 7.15 mH = 0.00715 H = 7.15e-3 H.
But never use the unit symbol as part of the value, or you will find that a 1F capacitor has a capacitance of only one femtofarad.
In SPICE, M is also milli, but avoid the use of upper-case M, except as the first letter of Meg = 1e6.

6. How is the behavior of the voltage divider with the parallel capacitors different/better than just one or the other.
The resistors maintain the DC which is important for a zero crossing detector or an oscilloscope. The capacitors give it the wide bandwidth required to avoid phase shifting fast signals. The parallel combination keeps the phase shift zero, and the frequency response flat, all the way from DC to daylight.

7. How do I open the .plt file for viewing?
When you 'Run' the simulation, LTspice uses it to generate the plot window traces and colours. It is written when you 'file', 'save plot settings'.
You can look inside using a text editor, but don't edit it by hand.

 

[Baluncore]

4. How is setting the V(a) condition changing the analysis much other than setting the initial voltage to 240? Is it necessary? In reality, aren't both voltages really zero in the beginning?

When in LC resonance, current in the inductor is in quadrature with voltage on the capacitor, so they are never zero at the same time. If they both start the simulation at zero, it takes about 40,000 cycles of oscillation before the circulating energy builds up, and the voltage becomes symmetrical about zero. I avoid that simulation settling time, by starting the capacitor with a non-zero voltage.
It is like pulling a child back on a swing, then letting them go, to get things moving quickly.

4b. How did you enter the label "a"

Menu 'edit', 'Label Net'. Shortcut F4, or the 'Label Net' button in the toolbar, between the ground and resistor icons.

 

[TonyStewart]

Some imperfections to simulation may include:
- k coupling coefficient won't be exactly 1 and the leakage becomes the mutual inductance L4 a series fraction of primary inductance and dampens the resonance.
- V1 source must include RdsOn of FETs or added as a discrete R.
- L2 has no resistance but may be added by default settings for some L/R ratio.
- using 0 to 200V primary has the disadvantage of adding reducing L from saturation and +/-100 V removes that DC current offset.

 

[imsmooth]

My goals is to get a good zero crossing trace for my capacitor voltage. I was able to get a good noise-free signal with an optocoupler I had lying around. The violet trace is the output when analyzing the capacitor voltage (not shown on the scope).

The problem is that I need a resistor to limit the maximum current to the LED to 25ma, which increases the voltage necessary to get the coupler to start detecting a lower voltage.

I'm trying to go through the data sheets on mouser and digikey to find one that has fast switching, low turn-on voltage, minimal propagation delay and a diode that can tolerate a higher current to give me the ability to detect a voltage ranging from 0-500Vrms.

Any suggestions for a good optocoupler/isolator?

 

[Baluncore]

My goals is to get a good zero crossing trace for my capacitor voltage.

Why, or what will you use the signal for?
You need to write some specifications. How do you define "good" ?

An optocoupler and resistor is not the solution if you want a crisp edge at the right time. An optocoupler will always switch a few volts late, while resistor current will be lowest, just when you need it to be greatest, and greatest when you want it to be lowest.

There are many solutions, each with its own pros and cons.

It seems you do not want a pulse on crossing, but a square wave that is in phase with capacitor polarity. How close to in phase?
Do you require symmetry, or can the wave have a fast rising edge with a slower falling edge?

 

[TonyStewart]

You must learn to define acceptance criteria.

https://tinyurl.com/2qt2ee2r

 

[imsmooth]

I just seem to go deeper into the rabbit hole.

Baluncore, you are right. I don't want pulses on zero crossing, but a square wave that closely matches the polarity of the capacitor, Symmetry would be preferred.

Tony, the Falstad applet was really nice. I'm sure much of what I think is wrong so I am ready hear the right answer:

I thought the purpose of the isolator was so two dissimilar circuits could get "linked". The diode simply needs current from a closed loop to turn the other side on and off. Why does the left side of the circuit need to share a ground? Can't I run the left side with a non-grounded, floating sinusoidal voltage source?

Also,
1. What's the purpose of the schottky diode? When I delete it nothing seems to change.
2. What is the purpose of the 1M on top of the 100pF capacitor in parallel? You have capacitance 100:1 divider.How are you are picking the value of the resistor to go with the 100p capacitor?

 

[TonyStewart]

The 100 pF was a current limiter voltage divider. The 1Meg and clamp diode were redundant for a unipolar signal 0 top 400V.

now I AC coupled reduced current to <4mA and phase shifted diode current 90 deg. The 10k senses current limited by the C reactance with some tiny fringe effects on duty cycle.

duty cycle is 50% +/-2 https://tinyurl.com/2pyrb6a2

 

[imsmooth]

In both of your applets will the isolator's diode work when the AC source voltage is very low? I see it works on the simulation. The issue I was having was at low voltages there was not enough current to turn the isolator's diode on.

Also, the phase error addition aside, what is the functional difference between the two applet's output?

 

[TonyStewart]

When input current is low, you raise collector R value the same and buffer as I did. The diodes capacitance is not modelled so there are freq. limits and also tolerances on hFE are not an option there.

Often the opto losses are near the hFE gain so you see the CTR specs. are near 1 or worst case maybe 10% and best case >> 100% but the biggest variable in production is hFE. (depending on p/n)

 

[Baluncore]

The diode, in antiparallel with the optocoupler LED, prevents destruction of the LED by reverse voltage.

The greatest slew-rate of the capacitor voltage is at the time of the zero-crossing. It would be sensible to use a capacitor to deliver the current needed to drive the optocoupler LED. The gating of that current through the optocoupler could be done by the capacitor voltage.

 

[TonyStewart]

The gating of that current through the optocoupler could be done by the capacitor voltage.

meaning:
Since I chose a small series C , its impedance being highest by far the 90 deg. Phase shift is dominated by Vc drop and < 1% by load= Vf/If +Rs, so the phase error is low.

Since the largest voltage drop is across C and current sensed by the real R (albeit nonlinear diode effect, it is still real R. for the most part neglecting low current diode capacitance)

In the initial divider we had matched R1C1 to R2C2 to get a wide spectrum voltage divider rather than the familiar partial derivative frequency response.

 

[imsmooth]

When input current is low, you raise collector R value the same and buffer as I did. The diodes capacitance is not modelled so there are freq. limits and also tolerances on hFE are not an option there.

You're referring to the 10k resistor as the current sense, right?. If the voltage goes up on the cathode side of the LED diode doesn't that decrease the voltage drop across the diode and hence the current driving it? When you say "raise" the collector R are you saying you choose different design values? My issue is the voltage source varies from 0 to 500Vrms and the value of R would be fixed.

 

[imsmooth]

The diode, in antiparallel with the optocoupler LED, prevents destruction of the LED by reverse voltage.

Would any hyperfast Schottky diode work?

 

[Baluncore]

Please do not edit inside a quote, because then we can't quote your post.
Click on the [ ] button to toggle BB code.

Would any hyperfast Schottky diode work?

Any diode would work. It only has to conduct the LED current, or withstanding a couple of LED forward volts.

 

[berkeman]

Please do not edit inside a quote, because then we can't quote your post.
Click on the [ ] button to toggle BB code.

(I fixed up the quote box, and sent him a PM about it)

 

[imsmooth]

meaning:
Since I chose a small series C , its impedance being highest by far the 90 deg. Phase shift is dominated by Vc drop and < 1% by load= Vf/If +Rs, so the phase error is low.

Since the largest voltage drop is across C and current sensed by the real R (albeit nonlinear diode effect, it is still real R. for the most part neglecting low current diode capacitance)

If I understand the model correctly, the series capacitor (and resistor) is limiting the current to a safe level for the optoisolator when the voltage is near the maximum. What happens when the voltage is near the minimum? There will not be enough current to drive the LED, right? If this is correct, is there anything that can be done so the circuit works over most of the input voltage range?

 

[TonyStewart]

You're referring to the 10k resistor as the current sense, right?. If the voltage goes up on the cathode side of the LED diode doesn't that decrease the voltage drop across the diode and hence the current driving it? When you say "raise" the collector R are you saying you choose different design values? My issue is the voltage source varies from 0 to 500Vrms and the value of R would be fixed.

Yes 10K does limit the peak current over a small range only.

You will never be able to detect a signal over a 40 dB dynamic range, unless you use AGC or an active current limiter. The opto is not the best choice for a dynamic input signal. Often these are done with PLL's and lock-in amplifiers or precision comparators with a high SNR signal and a wide CM in put range using the RC divider.
You need a high speed linear opto to saturate an open collector at 75 kHz at low output current, perhaps the 6N136 but with 47 k to 5V that is only Ic < 100 uA so with 10% CTR you need 1mA input.

So I would not recommend this approach if you are hunting for resonance and have no output. I would use an automatic hardware based linear resonant oscillator method that oscillates from phase of the attenuated output for AC feedback or a PLL.

 

[Baluncore]

@imsmooth10
If you need a zero-crossing detector to help auto-tune your generator and tank, you might consider two identical attenuators and a mixer or multiplier, followed by a low-pass filter. That makes a phase detector. If you multiply the drive voltage by the capacitor voltage, the average DC output from the LPF will be zero when tuned. The LPF output voltage passes through zero as the drive frequency crosses the LC resonant frequency. The detected voltage can be used to drive a motor, or software, to tune the drive or the tank.

 

[TonyStewart]

@imsmooth10
the average DC output from the LPF will be zero when tuned.( in a PLL)

Generally, the DC output in a linear phase mixer is 50% of the 180 degree output swing for the polarity that causes negative feedback. This may lock if the difference frequency is within the "capture range" of the PLL. The range of 180 to 360 degrees has the opposite triangle slope, causing positive-feedback, which pushes the VCO away. When capturing the time spent in positive feedback is push fast, so when negative it slows down and the average effect is to pull towards the same frequency and at 90 deg with DC and a 2f output. When outside the capture range, the feedback time is balanced for each phase, and it does not lock. The capture range is determined by the LPF BW and the VCO error f and loop gain with phase compensation filter. The mixers typically used are XOR gates, so the lock-in voltage is Vdd/2 using the CD4046 or equiv.

https://web.ece.ucsb.edu/~long/ece594a/PLL_intro_594a_s05.pdf

 

[Baluncore]

The mixers typically used are XOR gates, so the lock-in voltage is Vdd/2 using the CD4046 or equiv.

I do not suggest nor recommend an XOR gate, as that would be biased by the logic rail voltage and would require some form of voltage comparator on both inputs. My aim was to escape from the need for a comparator and the delay of the requisite high gain digital path.

The phase detection should be based on the amplitude of the sinewave over the period, rather than just the time of two switching edges from some hysterical quantifying logic.

That is why I suggested using an AC coupled analogue multiplier, an MC1496 Gilbert cell, or possibly an RF mixer. The output would be symmetrical about zero, so would be signal-gain and supply-voltage independent.

The phase of the lock of a PLL is quite irrelevant to the analogue solution. It is trivial to swap the differential inputs of an analogue multiplier, to compensate for an inverting miller-integrator in the LPF.

 

[TonyStewart]

I do not suggest nor recommend an XOR gate, as that would be biased by the logic rail voltage and would require some form of voltage comparator on both inputs. My aim was to escape from the need for a comparator and the delay of the requisite high gain digital path.

The phase detection should be based on the amplitude of the sinewave over the period, rather than just the time of two switching edges from some hysterical quantifying logic.

Facts from datasheets.
- The XOR gates may be capable of similar BW of Gilbert Cell useful for << 10MHz output.
- XOR gates do not introduce hysteresis and in quadrature are low noise and linear.
- PLL chips just use very high GBW of self-biased CMOS limiters
- single IC PLL's provide simplicity if tolerances are adequate.

 

[Baluncore]

Facts from datasheets.

Please identify the datasheets that make those statements, that you claim to be fact.

- The XOR gates may be capable of similar BW of Gilbert Cell useful for << 10MHz output.

An XOR is digital, a Gilbert cell is analogue, Gilbert cells work well at VHF frequencies.

- XOR gates do not introduce hysteresis and in quadrature are low noise and linear.

Voltage comparators introduce hysteresis.
How can an XOR logic gate be linear, z = a*(1-b)+b*(1-a) ?

- PLL chips just use very high GBW of self-biased CMOS limiters

I agree, they use self-biased CMOS inverting amplifier chains, to get within one volt of the supply rails, and then they revert to logic gates, inherently based on the time of the transitions.

- single IC PLL's provide simplicity if tolerances are adequate.

Anything is acceptable if you lower the requirements sufficiently. A marketing platitude, and a truism.