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sherrellbc
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I am having trouble figuring out how to design multistage amplifiers in general. I am working on a project in which I take the small signal from a condenser mic ( ± 5mV ), amplify and filter it a sufficient amount such that I can read into a microcontroller and process the information. I would like to use the full resolution of the Arduino due. (10bit, 5V), therefore an amplification of 1000 is needed.
I designed an input stage BJT common-emitter amplifier with a gain of approximately 50; the gain was actually 54. Then, I used an active filter to get the remaining 20 gain required to meet the spec of 1000. Now, both amplifiers work great if taken by themselves. The issue is that when I place the two stages in series,[STRIKE] my overall gain diminishes to about 800. [/STRIKE]The change that I noticed was that the input stage (the BJT) now has a gain of 84, [STRIKE]and the second stage dwindeled to about 9.6.[/STRIKE]
I realized I never changed the default rail supplies. The loading affect of the input stage's amplification increasing from 50 to 85 still persists. Can anyone help me to understand this? I now get 7.3V output. The associated gain is about 1460V/V. almost 1.5X what I designed for.
What am I missing here? I assumed it has something to do with loading the stages by placing them in cascade, but that reason is specifically why I included a buffering stage. The input resistance of the LM741 ( at 2kHz ) is approximately 9MΩ, and the associated input resistance is approximately 75Ω.I have attached the schematic used below.
Thank you.
http://tinypic.com/r/339sv8y/6
I designed an input stage BJT common-emitter amplifier with a gain of approximately 50; the gain was actually 54. Then, I used an active filter to get the remaining 20 gain required to meet the spec of 1000. Now, both amplifiers work great if taken by themselves. The issue is that when I place the two stages in series,[STRIKE] my overall gain diminishes to about 800. [/STRIKE]The change that I noticed was that the input stage (the BJT) now has a gain of 84, [STRIKE]and the second stage dwindeled to about 9.6.[/STRIKE]
I realized I never changed the default rail supplies. The loading affect of the input stage's amplification increasing from 50 to 85 still persists. Can anyone help me to understand this? I now get 7.3V output. The associated gain is about 1460V/V. almost 1.5X what I designed for.
What am I missing here? I assumed it has something to do with loading the stages by placing them in cascade, but that reason is specifically why I included a buffering stage. The input resistance of the LM741 ( at 2kHz ) is approximately 9MΩ, and the associated input resistance is approximately 75Ω.I have attached the schematic used below.
Thank you.
http://tinypic.com/r/339sv8y/6
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