555 timer, 50% duty cycle astable, run from 5V

[Baluncore]

Where is the pull up resistor connected when using the TTL version?

Between pin 3 output and V+ rail. Note that pin 7 can be an independent open collector output in that mode.
TTL outputs sink current from inputs. That means TTL output voltages do not need to go to the positive rail. Check the output voltage swing to select the PU resistor value.

 

[jim hardy]

For CMOS 555 timers, there is one that claims 50% duty cycle by connecting the cap to the divider chain with pins 2&5 (TRIGGER & CONTROL) tied together and the timing resistor fed from pin 3 (OUTPUT). I haven't tried it,

i've used that
it would be perfect if the output pulled pin 3 pull all the way to V+ and V-
but since there's headroom required that depends on load current
you have slight asymmetry in the charge and discharge paths.

TTL outputs sink current from inputs. That means TTL output voltages do not need to go to the positive rail. Check the output voltage swing to select the PU resistor value.

Yes !
IIRC the 555 has totem-pole output so it can sink or source 100 ma of current
http://www.ti.com/lit/ds/symlink/lm555.pdf

(EDIT - Well, as i said. 200 ma)
and you'd think output could drive to either rail

but it sinks better than it can source
it can source only to about a volt below positive rail in high state
but it'll sink almost to negative rail in low state

hence the asymmetry

a nice detail to be aware of...

old jim

 

[Matt Hall]

Old Jim is entirely correct. The output of the normal 555 never goes to the supply rails. That introduces errors which will not only result in asymmetry of the output waveform but will make the timings both supply voltage and load dependent. The CMOS version may be better in this respect, depending on the load.

The method of changing the thresholds which I described does not have those disadvantages. The output waveform barely changes with either supply voltage or load and symmetry can easily be achieved by tweaking the thresholds using the resistor from pin 5 to ground.

There are some minor disadvantages of my method. The 555 always has an inherent error in the length of the discharge phase (output low) caused by the small collector - emitter voltage of the discharge transistor (pin 7) and that gives a slight change in the timing of the output low phase with supply voltage. With reduced thresholds the effect of that error will increase somewhat. Likewise, the amount of jitter in the waveform timing will increase - a larger capacitor on pin 5 will help to keep that down.

If these disadvantages are a concern the best policy would be to have the 'charge' resistor (R1) much less than the 'discharge' resistor (R2) so that the thresholds need only be reduced slightly to achieve a 50:50 timing.

I have not seen the method I described in a manufacturer's data sheet (I certainly haven't read them all!) but a Signetics sheet from 1972 does show how to modulate the output high period by applying modulation to pin 5.

Matt

 

[jim hardy]

but a Signetics sheet from 1972 does show how to modulate the output high period by applying modulation to pin 5.

those old Signetics books are a treasure

see https://archive.org/details/bitsavers_signeticsdcsLinearVol1_11470058

table of contents

if you have room for a 100 meg document you'll love it. I just saved a copy to my PF folder.