- #316
kisch
- 3
- 0
kisch said:I get your point.
So I'm confident that the 100MHz clock is shared, and not generated on the front end boards, although I admit that this is not expressly stated in the paper.
Here's a confirmation for my view:
http://www.lngs.infn.it/lngs_infn/contents/lngs_en/research/experiments_scientific_info/conferences_seminars/conferences/CNGS_LNGS/Autiero.ppt" by Dario Autiero (2006).
Slide 8 and 9 describe the clock distribution system, and the master clock signal seems to be running at 10MHz.
In a http://www.docstoc.com/docs/74857549/OPERA-DAQ-march-IPNL-IN-CNRS-UCBL" by J. Marteau et al. (2002), the DAQ boards are described in detail.
On page 8, you can see that the boards don't contain any local oscillator.
Page 16 states:
"A fast 100MHz clock is generated by the FPGA using a PLL." (essentially from the 10MHz master clock signal).
This clock also drives the local CPU (an ETRAXX chip - the design was done in 2002).
Last edited by a moderator: